Disrupting the DRAM roadmap with capacitor-less IGZO-DRAM technology

A novel DRAM memory cell with two IGZO-based transistors The bit cell of dynamic random-access memory (DRAM), the main memory within traditional compute architectures, is conceptually very simple. It consists of one capacitor (1C) and one silicon (Si)-based transistor (1T). While the capacitor’s role is to store a charge, the transistor is used to access the capacitor, either to read how much charge is stored or to store a new charge. Over the years, bit cell density scaling allowed the industry to introduce subsequent generations of DRAM technology and cope with the growing demand for DRAM. But since about 2015, DRAM memory technology has struggled to keep pace with the performance improvement of the processor’s logic part: scaling, cost, and power efficiency issues form the building blocks of a rising ‘memory wall’. The large capacitor constrains scalability and 3D integration of the 1T1C bit cell, the ultimate path towards high-density DRAM. In addition, as the access transistor gets smaller, it provides an increasingly large leakage path for the capacitor’s charge to drain away. This lowers the data retention time and requires DRAM cells to be refreshed more frequently – impacting the power consumption. In 2020, imec reported a novel DRAM bit cell concept that can solve these two issues in one go: a bit cell made up of two thin-film transistors (2T, one for read, one for write) and no capacitor (0C) [1]. The conduction channel of the thin-film transistors is composed of an oxide semiconductor, such as indium-gallium-zinc-oxide (IGZO). Due to its wide bandgap, IGZO-based transistors have an extremely low off current, benefitting the memory’s retention time, refresh rate, and power consumption. The longer retention time also relaxes the requirement for the storage capacitance, allowing the parasitic capacitance of the read transistor to take over the role of the storage element. In addition, fabricating an IGZO 2T0C bit cell is simpler and more cost-effective than traditional cells. Other than Si, IGZO material can be deposited at relatively low temperatures, making it compatible with back-end-of-line (BEOL) processing. This opens doors to new DRAM architectures. First, it allows the DRAM periphery – the logic transistors that enable the full functionality of the DRAM chip – to be moved under the DRAM memory array instead of residing next to it. This reduces the footprint of the DRAM memory chip and makes connections between the array and periphery more efficient. In this configuration, the 2T0C DRAM bit cells are integrated into the peri’s BEOL, which is allowed by the properties of the IGZO material. Second, the novel bit cell paves the way for stacked configurations, providing an additional increase in density. Either ‘2D’ or ‘true 3D’ stacking can be envisioned. With 2D stacking, several layers with ‘planar’ DRAM memory arrays are stacked on top of each other. With 3D stacking, the transistors that make up the 2T0C bit cell are stacked and monolithically integrated into vertically aligned plugs inspired by 3D NAND technology. The ability to deposit IGZO conformally in these high-aspect-ratio plugs, enabled by the technique of atomic layer deposition (ALD), is a key enabler of this 3D structure. These stacked configurations will help tear down the memory wall, allowing DRAM memories to continue playing a crucial role in data-intensive applications such as cloud computing and artificial intelligence. Implementing the two transistors on different levels (stacked 2T0C) has an additional benefit. A low-off-current oxide semiconductor channel is only fundamental in the write transistor to ensure long retention. For the read transistor, on current is the critical parameter, as it drives the read time, and high-mobility channel materials can be considered. The two transistors can thus be optimized separately. First ‘conceptual’ demonstration of an IGZO 2T0C DRAM bit cell After pioneering the concept, imec provided the first experimental demonstration of a functional 2T0C DRAM cell at the 2020 IEEE International Electron Devices Meeting (IEDM) [1]. Thanks to a low (extracted) off current of 3x10-19A/µm, these first 2T0C DRAM cells exhibited a retention time >400s, about 1,000 times longer than typical DRAM refresh times. The results were obtained after scaling and optimizing IGZO-based thin-film transistors processed on 300mm wafers. Optimizations were directed towards suppressing the impact of oxygen and hydrogen defects, one of the main challenges for developing good-performing IGZO-based transistors. Optimized transistors with a 45nm gate length were then integrated into a 2T0C DRAM bit cell architecture, where the parasitic capacitance of the read transistor served as the storage element.