Computing’s Top 30: Sukanta Dey

Sukanta Dey’s cutting-edge work in areas such as electronic design automation (EDA) and integrated chip (IC) creation is fueled, in part, by awe. Awe that billions of transistors can be integrated onto a single chip. And awe that something as mundane as grains of sand can be transformed into advanced microchips that power everything from smartphones to pocket-sized ultrasound scanners. While the blend of physics, engineering, and computation required to achieve all of this is what inspires Dey, what drives him is a desire to push the boundaries of what’s possible in his field. Dey is a senior EDA software engineer at Intel. His innovative work and professional commitment earned him a spot among Computing’s Top 30 Early Career Professionals for 2024. In the following Q&A, Dey describes How his contributions to EDA—including his original research on machine learning approaches for EDA—led to his being awarded an O-1A visa. Aspects of his work at Intel, which includes enhancing automation in the custom IC design flow to reduce the repetitive tasks required of designers so they can better focus on creativity and innovation. His popular YouTube video on machine learning for VLSI CAD, which was inspired by his desire to make cutting-edge research in machine learning for VLSI CAD accessible to researchers and to industry professionals. His lessons learned on the career path so far, which include that nothing beats hard work, a relentless pursuit of excellence, and a “never going to give up” attitude. You were awarded the DesignCon 2024 “40 Under 40” Award. What key projects or contributions led to this recognition, and how has it impacted your career? I was honored with DesignCon 2024’s 40 Under 40 Award in recognition of my contributions across multiple domains of chip design. These include my PhD research on machine learning for VLSI CAD; my postdoctoral work on secure physical design; and my contributions at Intel, where I have worked on various design solutions for the Custom IC Design flow, specifically in physical design, physical verification, and parasitic extraction. The award recognition has provided me with the opportunity to interact and network with professionals who share similar interests at the DesignCon conference. Engaging with experts in chip design has allowed me to exchange ideas, foster collaborations, and contribute to the advancement of the field. Receiving the O-1A U.S. Visa for extraordinary abilities in the EDA domain is a significant achievement. What were the key factors that contributed to this recognition, and how has it influenced your professional journey? The O-1A visa is awarded to individuals with extraordinary abilities in their respective fields, and receiving it has been a significant milestone in my professional journey. Key factors that contributed to this recognition include my consistent contributions to the field of EDA. I have published original research on machine learning approaches for EDA, which has been widely cited, highlighting its impact on the global EDA community. Additionally, I have served as a reviewer for several prestigious journals and conferences, actively contributing to the advancement of research in this domain. My role as a technical program committee (TPC) member at various conferences further reflects my commitment to shaping the future of EDA. You have led several initiatives at Intel, including enhancing custom IC design and automating domain regression. Can you discuss a recent project you worked on and the innovative techniques you used? Most of my projects at Intel involve confidential work, but I can share that my primary motivation has been to simplify the workflow for analog designers while achieving higher performance, power, and area (PPA) with reduced turnaround time. A key focus of my work has been on enhancing automation in the custom IC design flow, particularly in physical design, physical verification, and parasitic extraction. By leveraging advanced scripting, AI-driven optimizations, and innovative tool integrations, I have contributed to improving design efficiency and reducing manual effort. These solutions help designers focus on creativity and innovation rather than repetitive tasks, ultimately accelerating the path to high-quality silicon. Your research has been published in top EDA journals and conferences, including Transactions on Design Automation of Electronic Systems (TODAES) and Design, Automation, and Test (DATE). What drives your passion for research, and how do you stay motivated to continuously contribute to the scientific community? The very fact that billions of miniaturized transistors can be integrated onto a single chip, enabling powerful computations at our fingertips, fascinates me about the field of VLSI, EDA, CAD, and chip design. Even more astonishing is the transformation of something as simple as sand into a highly sophisticated microchip that can power everything from smartphones to video game consoles. This remarkable blend of physics, engineering, and computation continues to inspire me. My passion for research stems from the drive to push the boundaries of innovation in this field. The challenge of developing smarter design methodologies, improving automation, and enhancing the efficiency of modern semiconductor devices keeps me motivated. Contributing to the scientific community through publications in top EDA journals and conferences allows me to share knowledge, collaborate with like-minded researchers, and play a role in shaping the future of chip design. You created a YouTube video on machine learning for VLSI CAD, which garnered over 2.5K views. What inspired you to create this video, and how do you approach making complex topics accessible to a broader audience? This video was essentially a recording of one of my conference talks, which received significant attention within the chip design community. My inspiration for creating this video stemmed from a desire to make cutting-edge research in machine learning for VLSI CAD more accessible to both industry professionals and researchers. When presenting complex topics, I focus on breaking down technical concepts into intuitive explanations, using real-world analogies and visualizations whenever possible. I also structure the content in a way that gradually builds on fundamental principles, making it easier for viewers with varying levels of expertise to follow along. Seeing the positive response to the video has reinforced my belief in the importance of knowledge sharing, and I look forward to creating more content that bridges the gap between advanced research and practical applications in chip design. Reflecting on your career journey—from your education at IIT Guwahati to your roles at the University of Florida and Intel—what are key lessons you have learned, and how have they shaped your approach to innovation and leadership? One of the most important lessons is that nothing beats hard work, dedication, and determination. A relentless pursuit of excellence, coupled with a “never going to give up” attitude, has been crucial in overcoming challenges and driving innovation. Passion for the domain is another critical factor; true breakthroughs happen when you deeply love what you do. Additionally, collaboration and continuous learning have played a significant role in my growth. Engaging with experts, mentoring others, and being open to new ideas have helped me refine my problem-solving skills and contribute more effectively to cutting-edge advancements in chip design and EDA. Leadership, to me, is about inspiring others, fostering a culture of curiosity, and driving impactful solutions. By staying adaptable and embracing new technologies, I continue to push boundaries in this ever-evolving industry. Your PhD work focused on using AI/ML techniques to automate the power grid design flow. Can you discuss the main findings of your thesis and their implications for the EDA industry? Using AI/ML techniques to automate the power grid design flow is a critical aspect of chip design. At the time I wrote my thesis, large language models were not as prominent as they are today—and chip design was far from being a fully automated process by AI/ML. Even now, despite advancements in AI, chip design remains a complex process that cannot be entirely replaced by machine learning. One of the key findings of my thesis was that machine learning alone is not sufficient for effective chip design. While AI can certainly automate parts of the design process, the integration of classical numerical methods and optimization techniques is necessary to achieve optimal design solutions. Machine learning models are highly dependent on the quality and quantity of training data, and generating reliable data for chip design is a substantial challenge. Therefore, combining data-driven machine learning approaches with traditional numerical methods yields the most effective results in chip design. This hybrid approach helps leverage the strengths of both methodologies, ensuring that we can navigate the complexities of scaling technology while maintaining the quality and efficiency of the design process. These findings have significant implications for the EDA industry, as they highlight the need for a more integrated approach that combines both AI/ML and classical techniques to tackle the increasingly complex design challenges in modern chip development. As a senior EDA tools software engineer at Intel, you work on various aspects of custom IC design. How do you approach problem-solving and innovation in this role, and what are the key challenges you face? My approach to problem-solving and innovation is rooted in a combination of analytical thinking, collaboration, and a deep understanding of the underlying technologies. When tackling complex issues in custom IC design, I break down the problem into manageable parts, identify root causes, and explore potential solutions from different angles. I rely on a mix of rigorous testing, simulation, and data analysis to validate these solutions and ensure their practicality. Innovation in this role often comes from identifying opportunities for automation, optimizing workflows, and improving efficiency in the design process. I actively explore emerging technologies, such as AI and machine learning, to enhance design tools and improve PPA metrics. Collaborating with cross-functional teams also plays a crucial role in driving new ideas and ensuring that we’re solving real-world problems for our designers. Key challenges I face include dealing with the ever-increasing complexity of modern custom IC designs, managing tight deadlines, and ensuring that our solutions scale effectively across various design processes. Additionally, the need to continuously stay ahead of technological advancements and integrate new methodologies into existing workflows presents an ongoing challenge, but it’s one that drives constant innovation in the field. You have worked on projects related to security closure of physical design and IR drop and electromigration sign-off for on-chip power grid design. Can you discuss the importance of these projects and their impact on the reliability and security of integrated circuits (ICs)? The projects I’ve worked on related to IR drop, electromigration sign-off, and security closure in physical design are crucial to ensuring the reliability and security of ICs. IR drop refers to the voltage drop that occurs when current flows through interconnects. In a chip design—and especially when power pads are located at the boundaries—IR drop can become significant toward the middle of the chip. This voltage reduction can lead to timing issues and negatively affect the design’s operating frequency, potentially causing the circuit to malfunction. To mitigate these risks, it’s essential to reduce IR drop violations by optimizing the design, ensuring that the chip’s power distribution network is capable of delivering a stable voltage to all components. Electromigration, on the other hand, is a phenomenon where the momentum transferred from electrons to metal atoms over time causes the displacement of these atoms, leading to the creation of voids and hillocks in the metal interconnects. This degradation is more pronounced in areas of high current density and can lead to the failure of the chip. To prevent electromigration-related failures, it is necessary to optimize the design, reducing current densities in vulnerable areas and improving the robustness of the interconnects. Both of these phenomena are critical to ensuring that the ICs operate reliably over time, particularly as the size of transistors continues to shrink and current densities increase. In addition to electrical reliability, ICs are subject to numerous security threats, such as information leakage, side-channel attacks, fault injections, malicious changes, reverse engineering, and piracy. Many of these attacks exploit vulnerabilities in the physical placement and routing of cells and interconnects. While several measures have been proposed to address security concerns at higher levels—such as functional design and logic synthesis—it is equally important to incorporate security sign-off during the physical design flow. This ensures that the chip is secure end-to-end, from design through fabrication, and that vulnerabilities are mitigated early in the design process rather than later, when they may be more difficult or costly to address. These projects are essential for creating robust, secure, and reliable ICs that can withstand both operational stresses and security threats, ensuring that modern semiconductor devices perform as expected and remain secure in the face of evolving challenges. Bio: Sukanta Dey Sukanta Dey is a senior EDA software engineer at Intel, Santa Clara. Previously, he was a postdoctoral research associate in the Department of Electrical and Computer Engineering at the University of Florida, Gainesville. He received his master’s degree and PhD from the Department of Computer Science and Engineering at the Indian Institute of Technology (IIT) Guwahati, specializing in machine learning techniques for EDA, which culminated in his PhD thesis, Design Methodology for On-Chip Power Grid Interconnect: AI/ML Perspective. Prior to joining IIT Guwahati, Dey received his bachelor’s degree in electronics and telecommunication engineering from Assam Engineering College. Dey’s domain of expertise includes EDA, VLSI CAD, VLSI physical design, machine learning for VLSI CAD, custom IC design (analog and mixed signal), RTL to GDS2 flow (ASIC design), and hardware security/security-aware EDA. His research has been published in prominent journals and conferences, including ACM TODAES, IEEE/ACM DATE, the IEEE Computer Society Annual Symposium on ISVLSI, and IEEE/ACM VLSI Design (VLSID). He has served as a technical program committee member, an expert reviewer, and an organizing committee member of various premier ACM and IEEE conferences, including Design Automation Conference (DAC), International Symposium on Hardware Oriented Security and Trust (HOST), and VLSID. He also serves as a research paper reviewer for IEEE and IET journals. Dig Deeper To learn more about Dey and his work, Checkout his GitHub page his publications on Google Scholar Connect with him on LinkedIn Over the next few months, Tech News will highlight different Top 30 honorees each week. For a full list, see Computing’s Top 30 Early Career Professionals for 2024. Looking for more insights into how to start, build, and sustain a thriving career? Visit the IEEE CS Career Center.