With AMD having attaining more than 40 percent revenue share and more than 27 percent shipment share in the X86 server CPU market in the first half of 2025, that means two things. First, AMD is selling some big, fat X86 CPUs compared to Intel. It also means that Intel, despite all of its many woes, is getting nearly 60 percent of revenues and north of 72 percent of shipments for X86 server CPU here in 2025.
No, that is not the share Intel is used to, but that’s life sometimes. And with the rollout of its “Clearwater Rapids” Xeon 7 P-core processor and the Xeon 7 “Clearwater Forest” E-core processors in 2026, everything hinges on the Intel 18A manufacturing process (what might otherwise be called 1.8 nanometers) as well as its 2.5D EMIB interposer and Foveros 3D chip stacking and bonding technologies, both of which saw their initial use in the datacenter on the ill-fated and much-delayed “Ponte Vecchio” Xe Max Series GPU accelerator.
To say that a lot is hanging on these two Xeon 7 processors is an understatement. With the hyperscalers and cloud builders ramping up the use of their homegrown Arm server CPUs, every X86 server socket in the datacenter is in contention, and AMD is a fierce competitor that has been metronomic in its regularity of Epyc server CPU launched and dominant because of the ability of Taiwan Semiconductor Manufacturing Corp to leapfrog over Intel Foundry’s processes and packaging.
But with 18A and the Xeon 7 next year, there is a chance for Intel to hold back the tide a little and perhaps reach an equilibrium with X86 server CPUs. While the E-core variants of energy-efficient, throughput processors are somewhat niche in their adoption, that is a good thing inasmuch as they will help Intel with ramping the 18A process as well as the 2.5D and 3D packaging techniques that are also expected with the P-core variants of the Xeon 7.
Those packaging challenges were enough for Intel to never promise Diamond Rapids for 2025 and for it to push out Clearwater Rapids to the first half of 2026, which it did in January before it had a new chief executive officer after letting Pat Gelsinger go. This delay may once again give AMD a chance to stay ahead of Intel.
Back in April, AMD was the first maker of a high end chip – in this case, a future “Venice” Epyc 9006 processor based on the Zen 6 core – to tape out on TSMC’s 2 nanometer N2 process. But Venice is not expected until next year, so there is no benefit for Intel to rush a product out to market early at possibly low yields that are more costly than just waiting a bit until yields are better.
There are easier businesses to be in than semiconductor design and manufacturing. . . .
In any event, at the Hot Chips conference this week, Don Soltis, an Intel Fellow and the Xeon processor architect, walked through the Clearwater Forest E-core processor. Soltis even had an early sample of the Xeon 7 E-core CPU back from Intel Foundry, which he had tucked into his shirt pocket. (We did not get a good zoom in on the chip, since we are attending Hot Chips remotely this year.) Here is a mockup of the Clearwater Forest socket, which will have to tide us all over:
Clearwater Forest starts with the 18A process, of course. The 18A process uses gate-all-around 3D transistors, which Intel refers to as RibbonFET and a big improvement over the FinFET transistor design. Intel pioneered FinFET 3D tri-gate transistors back in 2011 with its 22 nanometer process, and all processes between then and 18A – 14 nanometer, 10 nanometer (including the Intel 7 refinement) all the way down to Intel 3 (3 nanometer) – use FinFET transistors. The “Sierra Forrest” E-core Xeon 6 processor launched in June 2024 was made using Intel 3 as well as EMIB to link chiplets on a socket interposer, but it did not use Foveros 3D stacking.
The 18A process delivers 15 percent better performance at the same power and 30 percent better chip density at the same area as the Intel 3 process. The 18A process is married to a backside power delivery technique called PowerVia, which uses both sides of the silicon wafer to deliver data signals on the front side and power to the transistors on the back side. (Prior CPUs from Intel and others delivered power and signal on the front side.) The net result is that transistors are smaller and use less power than even their shrinkage would account for.
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