View the code on GitHub
Links to the other parts in this series:
Introduction
This is the first in a series of blog posts describing my experience developing a low latency 10G Ethernet core for FPGA. I decided to do this as a personal project to develop expertise in low latency FPGA design and high-speed Ethernet, as well as to experiment with tools and techniques that I could use full-time. As a small spoiler, the design has less than 60ns loopback latency, which is comparable to commercial offerings.
These posts will focus on the things that are likely different to a ‘standard’ design, as I believe this will be more interesting to the reader. Specifically:
The use of cocotb and pyuvm for verification
The techniques implemented to reduce packet processing latency
Analysis of commercially available low latency and ‘ultra’-low latency cores
Latency measurement results and comparison
Other techniques not implemented
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