In Austin, Texas, a former 1980s chip plant is being refitted into a next-generation research foundry. Backed by $1.4 billion from the Department of Defense under DARPA’s Next-Generation Microelectronics Manufacturing (NGMM) program, the facility will concentrate on 3D heterogeneous integration (3DHI), assembling multiple chip types and materials in a single package to push beyond the limits of conventional silicon design.
The ultimate goal of this project is to close the gap between laboratory innovation and production, a persistent “lab-to-fab valley of death” that has long constrained U.S. hardware startups and defense contractors. In five years, the program is expected to transition from federal funding to a self-sustaining business serving both national security and commercial customers.
The project is a joint venture between DARPA, the state of Texas, and the University of Texas at Austin’s Texas Institute for Electronics (TIE), which will operate the fab. Housed in a refurbished 1980s-era facility, it is designed to serve as an open-access manufacturing and prototyping hub for next-generation chips that blend silicon, gallium nitride, photonics, and other advanced materials.
“We are, frankly, a startup,” said Dwayne LaBrake, the CEO of TIE. “We have more runway than a typical startup, but we have to stand on our own,” during an interview with IEEE Spectrum.
Building a fab for ‘weird’ chips
(Image credit: Intel)
Traditional semiconductor fabs produce monolithic silicon wafers, optimized for high-volume runs of identical designs. The Austin plant will take the opposite approach. It is being developed for high-mix, low-volume production, enabling researchers and companies to experiment with unconventional architectures and materials that mainstream foundries cannot accommodate.
DARPA program manager Michael Holmes describes 3DHI as a potential “revolution in microelectronics.” Stacking silicon on silicon, he said, can yield roughly 30-fold improvements in performance compared to 2D chips, but combining dissimilar materials could unlock up to 100-fold performance gains.
Such stacking presents formidable challenges. Dissimilar materials expand and contract differently with heat, requiring sub-micron alignment and new bonding techniques. The TIE facility is developing a process design kit (PDK) and an assembly design kit (ADK) that will codify how these materials can be combined in three dimensions, essentially creating a new design rulebook for heterogeneous packaging.
To validate its processes, NGMM is producing three demonstration systems: a phased-array radar, an infrared focal plane array, and a compact power converter. Each integrates multiple chip types, targeting critical defense applications in sensing, imaging, and power control.
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