IBM has detailed its most significant quantum computing advances to date, revealing new hardware and software designed to push the limits of what today’s superconducting qubits can do. The announcements, made during IBM’s Quantum Developer Conference on November 12, include a new 120-qubit chip, updates to the Qiskit software stack, and a testbed architecture for running quantum error correction in hardware. Together, the new tools represent a serious step forward on the path to fault-tolerant quantum computing.
Nighthawk expands IBM’s hardware
At the center of IBM’s near-term roadmap is the Nighthawk chip, a 120-qubit superconducting processor built to execute deeper circuits more efficiently than its predecessors. The chip moves away from IBM’s earlier “heavy-hex” qubit layout and instead uses a dense square lattice design. Each qubit connects to four neighbors via tunable couplers, for a total of 218 coupler pairs. That marks a 20% increase in inter-qubit connections over IBM’s Heron chip and reduces the number of swap gates needed to implement complex entangling operations.
IBM says this increase in qubit connectivity directly translates into larger algorithmic workloads. According to IBM, Nighthawk will support circuits with 30% greater complexity than Heron while maintaining comparable fidelity. That estimate is based on live metrics from Heron-class machines already deployed in IBM’s quantum cloud, which recently achieved two-qubit gate fidelities above 99.9% for over 50% of the tested pairs. In benchmarking terms, the chip family reached 330,000 circuit layer operations per second (CLOPS), a 65% gain over its 2024 performance. IBM expects similar or better numbers from Nighthawk once it becomes available to the public.
The new processor will play a central role in IBM’s campaign to demonstrate a verified quantum advantage, which the company now says it expects to achieve by the end of 2026. To support that claim, it has backed the formation of an open “quantum advantage tracker,” inviting third-party researchers to test candidate workloads against classical baselines. Early example circuits from partners, including Algorithmiq and the Flatiron Institute, have already been submitted, focusing on observable estimation and constrained optimization problems.
IBM’s timeline includes further performance gains beyond the current 5,000-gate target. The company expects iterative improvements to push that figure to 7,500 gates in 2026 and 10,000 by 2027, without increasing qubit count. These are incremental steps, but they align with the broader strategy IBM has laid out for gradually improving fidelity and circuit depth while using real benchmarks to validate progress against classical solvers.
IBM Quantum Nighthawk's qubit plane includes 120 qubits arranged in a square lattice. (Image credit: IBM)
Loon lays the groundwork for fault-tolerance
While Nighthawk represents IBM’s best shot at a near-term quantum advantage, the company’s ambitions rest on a longer arc toward fault-tolerant quantum systems. IBM’s engineers believe they’ll get there by the end of the decade, and this week’s preview of the “IBM Quantum Loon” test chip hints at what that system might look like.
Loon is a proof-of-concept superconducting test chip built to validate the hardware components required for scalable quantum error correction. IBM says the processor will include architectural features such as long-range inter-qubit couplers — known as “C-couplers” — designed to enable the efficient implementation of quantum low-density parity-check (qLDPC) codes.
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