Well, we did it… we cracked 4MIPS on our TTL CPU.
I have to admit I’m both relieved and surprised. The key parts to achieving this was to decrease the latency for the instruction decode and also the flag register writing. The time to decode an instruction, perform a bit of math and then write to the flags was at around 270nS.
With the changes we made, the instruction decode had a radical reworking and the flag writing had some big changes as well, means we go this down to under 200nS.
Which means we are able to run the CPU Core at 4MIPS!
Which we’re both super pleased with.
However (you knew there was a “but” coming didn’t you?) the external display (text and RGB dot matrix) does sometimes “glitch” at 4MIPS, but at 2MIPs is rock solid.
It’s a good thing we added that “speed” switch flag which will let us swap between speeds.
Whilst the boards themselves needed no modifications, we did make a couple of mistakes and had to swap some OR gates for AND gates, thankfully the same pin outs, so we’re happy.
PJ5 CPU running at 4MIPS
The new instruction board includes a few new commands, things like storeimm which stores an immediate value to a location in memory (rather than a regular store which stores the value of a register to memory) and also more branch options, things like branch if greater, branch if less than and so on.
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