TSMC’s dominance in advanced packaging has hit a supply-side wall. With the company's advanced CoWoS packaging capacity booked out by flagship AI players such as Nvidia, AMD, and Google, second-tier ASIC vendors and major U.S. chipmakers are now exploring Intel’s EMIB and Foveros as alternative back-end options. That includes customers manufacturing logic at TSMC's Arizona facility, but seeking faster, domestic packaging pathways — something Intel’s Rio Rancho, New Mexico, site is already positioned to offer.
CoWoS remains technically superior. However, new reports have pointed to Intel picking up packaging interest from firms that are either blocked from accessing CoWoS or looking for a shorter route to production. TrendForce in particular notes that Intel has already begun packaging some customer designs originally scoped for TSMC CoWoS, and is seeing growing inbound interest from non-traditional clients as a result.
While performance obviously remains a paramount consideration, we’re at an inflection point in AI silicon production, and time-to-package is going to become an increasingly important deciding factor for many chipmakers.
Intel’s EMIB (Embedded Multi-die Interconnect Bridge) technology connects chiplets using tiny silicon bridges embedded directly in the package substrate, eliminating the need for a large silicon interposer. This reduces both cost and thermal complexity, especially for designs that don’t need the wide I/O bandwidth or power delivery footprint of full CoWoS. Intel’s Foveros technology, by contrast, vertically stacks dies using through-silicon vias or direct copper bonding. It offers high interconnect density and heterogeneous node integration, at the cost of more stringent thermal and yield considerations.
TSMC’s CoWoS-L remains the go-to option for high-performance AI GPUs and HBM-heavy accelerators. Its capacity, however, is finite. TSMC is planning larger interposer sizes of up to 9.5x reticle by 2027, but that expansion is not arriving fast enough for the industry’s current volume requirements. Nvidia is increasing orders for H200 and B100 accelerators, both of which require extensive CoWoS packaging and high-stack HBM.
Intel has confirmed that some customer designs initially scoped for CoWoS have been ported to Foveros without modification. Its New Mexico facility, which handles both EMIB and Foveros packaging, is being scaled up by 30% and 150% respectively. Unlike TSMC, Intel’s packaging lines are not yet at saturation, and its U.S. location aligns with recent government funding and client interest in onshore manufacturing.
EMIB provides enough die-to-die bandwidth for inference accelerators, network ASICs, and other lower-bandwidth workloads, while sidestepping CoWoS’s cost and capacity constraints. It also supports integration with HBM via EMIB-T, which adds through-silicon vias (TSVs) for memory stacking without full interposers.
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(Image credit: Intel)
While Intel hasn’t formally named customers, MediaTek and Marvell were identified in recent reporting from DigiTimes as evaluating Intel’s packaging for second-tier AI ASICs. Both companies have existing ASIC roadmaps with inference-class acceleration and have previously worked with non-TSMC foundries.
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