Japan’s Dai Nippon Printing (DNP) claims to have developed a nanoimprint lithography template capable of patterning logic with a feature size of 1.4nm, with plans for mass production in 2027. Canon, which has spent years pursuing nanoimprint lithography as a lower-power alternative to EUV, is already shipping its first 300mm tools to early research partners.
Together, the companies are pointing to imprinting as a way to cut lithography power consumption by up to 90% for advanced nodes. With TSMC and Samsung preparing for 1.4nm mass production within the next few years, DNP’s announcement comes just as EUV’s cost and energy demands are escalating the fastest in leading-edge fabs. The technology promises a dramatic shift in the economics of chipmaking, but whether it can meet the defectivity, overlay, and throughput requirements of high-volume logic remains an open and pressing question.
Skyrocketing energy use
The industry has grown accustomed to talking about how much power finished AI chips consume, yet the energy needed to fabricate those chips has grown at a comparable pace. EUV scanners each consume as much power as a small city — 1,400 kilowatts per tool — meaning that modern fabs that run several dozen EUV units must reserve enormous electrical capacity before a single wafer is exposed. This rising power use is compounded by the fact that shrinking features below 2nm increase the number of passes and exposures required, raising energy consumption per wafer for next-gen high-NA EUV.
Canon, which has long argued that the industry needs an alternative, offers a nanoimprint lithography (NIL) system that patterns wafers by stamping a pre-formed template directly into resist rather than projecting a pattern optically. That equipment can be priced much lower than EUV, and Canon has claimed that the technology uses up to 90% less power. Just last year, the company delivered its first commercial FPA-1200NZ2C tool to the Intel- and Samsung-backed Texas Institute for Electronics, 20 years after NIL research began.
NIL has been looked upon with some skepticism in recent years due to its incompatibility with both DUV and EUV, and the more conventional view that NIL could not meet the overlay stability or defectivity requirements needed for tightly packed logic at sub-2nm geometries. DNP’s new template material is the first attempt to challenge that assumption with concrete specifications and a timeline to commercialization.
(Image credit: Canon)
The 1.4nm window
DNP’s template reportedly achieves 10nm line widths and is being evaluated ahead of planned mass production in 2027. Meanwhile, TSMC’s 1.4nm-class node is scheduled for risk production in the same year, with broader output in 2028, and Samsung has targeted a similar window. Both companies are expected to rely on EUV for the majority of patterning steps, but neither will be blind to the cost pressures. A secondary patterning pathway that reduces EUV load would be welcome, provided it clears the engineering hurdles.
Canon has pitched nanoimprint not as a replacement for EUV but as a complementary tool for specific layers and structures. Advanced patterning at sub-2nm often relies on techniques such as self-aligned double and quadruple patterning to extend resolution beyond single-exposure limits, and some researchers have explored how alternative lithography approaches, such as NIL, fit into these schemes. Nobody is claiming that a 1.4nm chip can be manufactured entirely through imprinting; rather, the proposal is that certain layers, currently exposed with EUV, could be transferred to a lower-cost, lower-power workflow.
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