AMD this week released a document titled "Performance Monitor Counters for AMD Family 1Ah Model 50h-57h Processors" (discovered by InstLatX64) that reveals numerous architectural details of AMD's Zen 6-based CPUs, including the EPYC 'Venice' processor for data centers, through performance monitoring interfaces. As it turns out, Zen 6 is not exactly an evolution of Zen 5, but rather an all-new design with a different ideology.
AMD has been talking about its Zen 6-based CPUs in very general terms for quite a while, revealing that they will feature up to 256 cores and be made using TSMC's 2nm-class process technology. This week's PMC document for software developers states that the Zen 6 microarchitecture is no longer an incremental evolution of Zen 4/Zen 5, but a deliberately wide, throughput-oriented design with an eight-slot dispatch engine and simultaneous multi-threading (SMT).
In such a design, two hardware threads dynamically contend for a shared pool of dispatch slots, so, at the same clock speeds, the single-thread performance of Zen 6-based processors may not be as high as that of Apple's 9-wide (or wider) CPUs in all situations. However, in some instances, this type of architecture promises very high performance. Furthermore, the core has dedicated counters for unused dispatch slots, backend stalls, and thread-selection losses, which confirms that wide issue and SMT arbitration are the factors AMD is betting on with Zen 6.
Zen 6 also substantially expands AMD's visibility into vector and floating-point execution, underscoring the architecture's emphasis on dense-math workloads. According to PMC documentation, Zen 6 processors support full-width AVX-512 execution with FP64, FP32, FP16, and BF16 data formats, including FMA/MAC operations and mixed FP-INT vector execution (including VNNI-class, AES, and SHA operations). Furthermore, it delivers sustained 512-bit throughput high enough to require merged performance counters for accurate measurement. This is hardly proof that Zen 6-based CPUs will be AVX-512 performance champions, but it does show that Zen 6 can retire enough vector work per cycle to overwhelm legacy measurement methods.
In general, Zen 6's performance-focused capabilities suggest it is AMD's first microarchitecture designed from the ground up for data center use cases. It remains to be seen which features will be retained in client offerings and how well these perform. But based on what we can observe today, Zen 6-based CPUs will be number-crunching monsters.
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