TSMC has quietly revealed that it had commenced volume production of chips using its N2 (2nm-class) fabrication process. The company did not issue a formal press release notifying about the production start, but the firm had said multiple times that N2 was on track for volume manufacturing in Q4, so the plan has been fulfilled.
"TSMC’s 2nm (N2) technology has started volume production in 4Q25 as planned," a statement at TSMC's web page dedicated to 2nm Technology reads.
(Image credit: TSMC)
From an improvement standpoint, N2 is designed to deliver a 10%–15% performance gain at the same power, a 25%–30% reduction in power at the same performance, and a 15% increase in transistor density compared to N3E for mixed designs that include logic, analog, and SRAM. For logic-only designs, transistor density is up to 20% higher than N3E.
Swipe to scroll horizontally Data announced during conference calls, events, press briefings and press releases. Compiled by Tom's Hardware Row 0 - Cell 0 N2 vs N3E N2P vs N3E N2P vs N2 A16 vs N2P N2X vs N2P Power** -25% ~ -30% -36% -5% ~ -10% -15% ~ -20% lower Performance*** 10% - 15% 18% 5% - 10% 8% - 10% 10% Density* 1.15x 1.15x ? 1.07x - 1.10x ? Transistor GAA GAA GAA GAA GAA Power Delivery Front-side w/ SHPMIM Front-side w/ SHPMIM Front-side w/ SHPMIM SPR Front-side w/ SHPMIM (?) HVM H2 2025 H2 2026 H2 2026 H2 2026 2027
*Chip density published by TSMC reflects 'mixed' chip density consisting of 50% logic, 30% SRAM, and 20% analog.
**At the same speed.
***At the same power.
TSMC's N2 is the company's first process node to adopt gate-all-around (GAA) nanosheet transistors, where the gate fully surrounds the channel formed by stacked horizontal nanosheets. This geometry improves electrostatic control, reduces leakage, and enables smaller transistors without sacrificing performance or power efficiency, ultimately increasing transistor density. In addition, N2 also adds super-high-performance metal-insulator-metal (SHPMIM) capacitors to the power delivery network. These offer more than twice the capacitance density of the prior SHDMIM design and cut both sheet resistance (Rs) and via resistance (Rc) by 50%, which improves power stability, performance, and overall energy efficiency.
"N2 is well on track for volume production later this quarter, with good yield," said C.C. Wei, chief executive of TSMC, during the company's earnings call in October. "We expect a faster ramp in 2026, fueled by both smartphone and HPC AI applications."
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