Japan’s state-backed foundry Rapidus plans to begin production of 2nm-class semiconductors in the second half of its fiscal year 2027, with full-scale production expected in 2028, according to a business plan submitted to Japan’s Ministry of Economy, Trade and Industry.
Manufacturing will take place at the company’s Chitose facility in Hokkaido, which is designed to support both front-end wafer fabrication and back-end processes, including dicing and packaging. Rapidus has stated that integrating these stages into a single facility will help streamline production and shorten turnaround times between processes and packaging.
Rapidus’ business plan (via Digitimes) claims that Chitose will begin output at 6,000 wafers per month, rising to roughly 25,000 per month within the first year of operation. That’s a modest goal for a mid-sized fab, but an especially tricky one to execute, as Rapidus is attempting to enter the most competitive segment of global semiconductor manufacturing for the very first time.
A rapid roadmap
Rapidus’ roadmap places the company in direct competition with other foundries targeting 2nm-class processes across a similar timeframe, and 1.4nm production in 2029. TSMC and Samsung have both outlined 2nm production plans around 2025 to 2027, while Intel is working on its own process under 18A.
The company’s initial 6,000 wafers per month would make it a relatively small-volume advanced-node supplier, and even the ramp-up to 25,000 wafers per month would remain below the peak capacities of leading-edge fabs operated by incumbents. It would, however, be sufficient support select high-performance logic customers, particularly in chiplet-based designs.
In order to achieve this, Rapidus must complete the installation and calibration of more than 200 tools to support 2nm production. These span lithography, etch, deposition, inspection, and metrology systems, and a coordinated ramp-up of these systems will be needed before yield stabilization can begin.
Speaking of yields, at 2nm, transistor architectures are primarily relying on gate-all-around structures, which increases fabrication complexity compared to previous FinFET nodes. Early yield shortcalls will significantly affect cost per die and customer qualification timelines, so yield performance and optimization will be a major focus for Rapidus. According to the Kyoto News report, achieving yield improvements through advanced process control is considered the most difficult hurdle for the company and could present a sticking point.
At 6,000 wafers per month, a modest yield shortfall could be absorbed as part of development, but at 25,000, every percentage point of yield directly affects gross margin and customer confidence. If early customers face unpredictable splits or wafer variability, it’ll be much harder for Rapidus to secure the volume commitments needed to make its 2nm operations commercially viable.
AI in the fab
... continue reading