Design and fabrication of the integrated modulator and modified UTC-PD
The TFLN modulator is fabricated on a 360-nm-thick X-cut single-crystalline LN thin film bonded on a 2.5-µm silicon dioxide layer sitting on a quartz substrate (NanoLN). First, the LN waveguides and multi-mode interference structures are patterned by positive resist by means of electron-beam lithography and etched by fluorine-based reactive ion etching. After the first lithography and etching, the LN waveguides with a sidewall angle of 72°, slab thickness of 180 nm and rib height of 180 nm are obtained. The slab is then patterned and etched to form the edge couplers. After patterning the LN waveguides and edge couplers, a plasma-enhanced chemical vapour deposition SiO 2 film of thickness 1.2 µm is deposited as the cladding layer. Subsequently, a 180-nm-thick NiCr layer is deposited as the terminal resistor and on-chip terminator. Next a lift-off process produces the 1-µm-thick gold transmission lines and DC electrodes. Finally, the device end face is diced, lapped and polished to achieve improved end-face coupling efficiency. The fabrication also complies with standard lithography and etching techniques available in a typical foundry, ensuring process reproducibility and potential for scalability.
The epitaxial structure of the modified UTC-PD is designed for high-speed and high-power operation. The 180-nm InGaAs absorption layer includes an 80-nm undepleted region with a step-graded profile (5 × 1017, 1 × 1018 and 2 × 1018 cm−3) to form a quasi-electric field that assists electron transport and the remaining 100 nm is depleted to establish a high electric field across the InGaAs/InP heterojunction. Beneath the absorber, a 220-nm slightly n-doped (1 × 1016 cm−3) InP drift layer is incorporated to support high-speed carrier transit. A 30-nm heavily doped (2 × 1017 cm−3) InP cliff layer is inserted between the absorber and the collector to sustain an electric field of 20–50 kV cm−3 in the drift layer to support electron velocity overshoot, thereby accelerating electron transmission and extending device bandwidth. The implementation of the cliff layer also greatly reduces the conduction band barrier across the heterojunction in the depletion region, thus suppressing carrier pile-up under high optical input and improving high-power performance. To further suppress parasitic capacitance and enhance RC-limited bandwidth, a 4-µm-thick benzocyclobutene dielectric layer is introduced beneath the coplanar waveguide electrodes, improving electrical isolation and device robustness. Moreover, the InP drift layer is extended outward to serve as the upper cladding of the InGaAsP waveguide, ensuring uniform optical absorption and mitigating localized saturation under strong light injection. Also, the thickness and refractive index of the 400-nm InGaAsP waveguide layer is carefully engineered to enable efficient and smooth evanescent light coupling into the absorber. This results in a more evenly distributed light absorption and carrier generation profile across the absorber, which mitigates localized saturation and enables higher output power under strong light injection.
The fabrication of the modified UTC-PD begins with the epitaxial growth on a 2-inch semi-insulating InP substrate using metal–organic chemical vapour deposition. The epilayers are similar to the structure in ref. 17. Ti/Pt/Au metal layers are then deposited to form the p-type ohmic contacts. The triple-mesa structure of the device is defined through a combination of inductively coupled plasma dry etching and selective wet etching. The etch process is precisely controlled to ensure accurate patterning, enabling close agreement between optical simulations and the fabricated device. Subsequently, Ge/Au/Ni/Au layers are deposited to form the n-type ohmic contacts, followed by rapid thermal annealing at 360 °C to enhance contact performance. Finally, a 3-µm-thick layer of benzocyclobutene is applied to provide passivation and mechanical support, following which Ti/Au coplanar waveguides are deposited to connect the electrodes to the PD contacts. The process flow uses a standard III–V semiconductor process and is compatible with wafer-scale manufacturing.
Characterization of the EO/OE response of the TFLN modulator and modified UTC-PD
We use a function waveform generator (RIGOL DG922 Pro) to generate a 100-kHz triangular voltage sweep and measure the V π,LF as 5.1 V by a digital oscilloscope (RIGOL DHO1202U). The V π,RF can then be calculated using:
$${V}_{{\rm{\pi }},{\rm{RF}}}={V}_{{\rm{\pi }},{\rm{LF}}}\times {10}^{-\frac{\text{EO}{S}_{21}}{20}}$$ (1)
As for the EO bandwidth characterization, measurements are conducted in three steps. First, a vector network analyser (Keysight N5222B) equipped with a millimetre test set (Keysight N5292A) and a LCA (Keysight N4372E) is used to generate and analyse frequency signals below 110 GHz. For higher frequencies, THz signals >110 GHz are generated by upconversion. The 250-kHz to 20-GHz signals (Keysight E8257D) are upconverted by frequency multipliers into the 110–170-GHz band (NZJ SGFE06) and the 140–220-GHz band (NZJ SGFE05) and then delivered to the TFLN modulator by means of matched ground–signal–ground (GSG) probes. EO response is measured by tracking the power ratio between the sideband and the carrier at each frequency using an optical spectrum analyser (OSA; Yokogawa AQ6370D). The normalized sideband power P n is defined as:
$${P}_{{\rm{n}}}=\frac{{P}_{{\rm{carrier}}}}{{P}_{{\rm{sideband}}}}$$ (2)
The V π,RF at each frequency can be calculated directly using equation (3) (ref. 50):
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