Major update to custom chipset emulation. Internally almost everything in main chipset emulation has been rewritten.
Fastest possible/JIT mode chipset timing/sync had major changes which can cause side-effects.
Bugs are very possible, especially in very rarely used features.
Custom chipset rewrite
Custom chipset emulation (Agnus/Alice and Denise/Lisa) almost completely rewritten. Almost every part of chipset emulation is now internally cycle accurate.
Custom chipset Denise/Lisa emulation is now running in separate thread for large performance increase in accurate emulation modes compared to previous versions.
VPOSW/VHPOSW tricks are now cycle-accurately emulated without restrictions.
Horizontal and vertical blanking and sync start/end, csync, csync equalization pulses, etc are now fully cycle-accurately emulated, both hardwired and programmed. Mixing of hardwired and programmed is fully supported. Agnus/Alice hardwired PAL/NTSC sync generator is almost logic gate level emulated.
“Display” and Agnus/Alice vertical and horizontal counters are now fully separately emulated, display emulation now works correctly even if Agnus vertical or horizontal is moved backwards or forwards or anywhere (even outside of normal display range), unlimited times per line and/or field.
All screenmodes (including “Fake” NTSC or similar mode) now count total number of “display” lines and uses it to setup display height. These modes now work even if they do multiple V(H)POSW modifications.
... continue reading