TSMC unveils plans for giant AI chips to meet surging compute demands

Serving tech enthusiasts for over 25 years.TechSpot means tech analysis and advice you can trust The big picture: The semiconductor industry is approaching a significant milestone as TSMC prepares to expand the physical scale of its chip packaging technology. At its recent North American Technology Symposium, the company detailed plans for a new generation of CoWoS (Chip-on-Wafer-on-Substrate) technology, enabling the assembly of multi-chiplet processors much larger than those currently in production. Today's high-end processors, especially those powering data centers and AI workloads, already rely on multi-chiplet designs to meet soaring demands for performance and memory bandwidth. TSMC's current CoWoS solutions can accommodate interposers up to 2,831 mm², more than three times the size of a standard photomask reticle, which is limited to 830 – 858 mm² by EUV lithography constraints. This technology is already being used in products like AMD's Instinct MI300X and Nvidia's B200 GPU ... Read full article.