GoKawiilIBM and Lam Research have announced a five-year research collaboration to develop the materials and fabrication processes needed to scale logic chips beyond 1nm using high-NA EUV lithography and Lam's Aether dry resist technology. The work will take place at IBM Research's NY Creates Albany NanoTech Complex in New York, with Lam's Aether dry resist technology at the center of the effort alongside its Kiyo and Akara etch platforms and Striker and ALTUS Halo deposition systems.
The two companies have collaborated for over a decade on 7nm process development, nanosheet transistor architecture, and early EUV process integration. Notably, IBM unveiled what it described as the world's first 2nm node chip in 2021, marking a significant milestone in the ongoing partnership.
Under the new agreement, the focus will shift to validating full process flows for nanosheet and nanostack device architectures and backside power delivery, using Lam's Kiyo and Akara etch platforms, Striker and ALTUS Halo deposition systems, and Aether dry resist.
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Aether and high-NA EUV
Standard EUV lithography utilizes chemically amplified resists, which are spin-coated onto wafers and developed using wet chemistry. That approach, however, has a fundamental problem at the geometries high-NA EUV scanners are designed to print: stochastic noise. This is a statistical variation in photon absorption per unit area, which drives defect rates up as features shrink.
Aether’s process, however, sidesteps wet chemistry entirely by depositing the resist via vapor-phase precursors and developing it using plasma-based dry processes. According to Lam, its metal-organic compounds absorb three to five times more EUV light than conventional carbon-based resist materials, reducing the exposure dose required per wafer pass and keeping single-print patterning viable at nodes where wet-process alternatives would require more expensive multi-patterning.
Fewer process steps between exposure and etch also reduce the number of points at which pattern fidelity can degrade, which is a compounding advantage as geometries continue to tighten. The renewed collaboration between IBM and Lam is specifically focused on proving that Aether can get high-NA EUV patterns reliably transferred into real device layers at production yield. Ultimately, that’s what needs to be done before sub-1nm processes can credibly move toward a production fab.
Nanosheet transistors, which stack multiple thin sheets of silicon to increase drive current without widening the transistor footprint, are one of the primary device architectures the teams will be validating. IBM’s press release also confirms work on nanostack devices and backside power delivery, which routes power connections through the back of the wafer rather than the front, freeing up front-side metal layers for signal routing and reducing the resistance losses that compound at high transistor densities.
Three deals in 14 months
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