GoKawiilAMD's position in the data center market has changed drastically in recent years: The company transformed from being an underdog, supplying less than 1% of server CPUs in 2017, to commanding nearly 29% of the server CPU market as of late 2025.
After increasing shipments of processors for data centers by several orders of magnitude in less than 10 years, AMD is changing the way it approaches the market in a bid to continue expansion. On the AI front, AMD is switching to an annual cadence of new product releases, and the company is doing the same for traditional data center CPUs.
Over the next 24 months, AMD is set to introduce the Zen 6-based EPYC Venice CPU with up to 256 cores in 2026, EPYC Verano processor in 2027, the Instinct MI400-series AI and HPC accelerators in 2026, which will power the Helios rack-scale solution for AI. It will also release the Instinct MI500-series AI and HPC GPUs in 2027, which will serve as the base for the company's next-generation rack-scale AI system.
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Launching around half a dozen major product designs, including several specialized CPUs and two rack-scale solutions, is a big deal. So let's go over AMD's data center roadmap for 2026 and 2027.
2026 CPUs: Venice and Venice-X — featuring up to 256 Zen 6 cores
AMD's upcoming sixth-gen EPYC Venice processor will rely on the company's next-generation Zen 6 microarchitecture and will also be the firm's first data center design to be made on TSMC's N2 (2nm-class) process technology. The chip will scale up to 256 high-performance Zen 6 cores, a 33% increase over the current EPYC Turin processors that feature up to 192 Zen 5c (compact cores).
AMD's EPYC Venice processor, as shown off at CES 2026, flush with the new SP7 form factor. (Image credit: AMD)
AMD's next-gen EPYC CPUs are expected to adopt the all-new SP7 form factor, which can accommodate more compute complex dies (CCDs) on the package, increase the number of memory channels, enhance I/O capabilities, and boost peak power delivery to feed extra cores.
In addition to the increased core count, another key improvement will be a major boost in memory bandwidth; EPYC Venice will provide up to 1.6 TB/s of per-socket memory throughput, more than doubling the 614 GB/s available on current EPYC CPUs. While AMD has not detailed the mechanism behind this increase, it is likely to involve support for advanced memory modules such as MR-DIMM or MCR-DIMM, which are becoming the default choice for CPUs with large core counts that are starved for sufficient memory bandwidth.
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