GoKawiilPlacing chips on a PCB is a difficult and consequential task. The way you place chips dramatically impacts how difficult it will be to route the PCB. There are signal integrity and power management issues with creating long paths between different components. The size of the PCB or where ports appear often is a design requirement that has to be considered and in some cases- pushed back on.
How does automatic placement fare? If you use a regular packing algorithm that minimizes the space usage, you will create a board that is nearly impossible to route. If you use a force-directed packing, where the netlist forms springs that pull chips close together based on their connections, you’ll get an unusual shape and suffer local minimums (it’s also wildly unpredictable)
An example component placement, considering the direct-path length of each trace that will need to be created
When we’re thinking about packing algorithms, the first concern should be capturing human design requirements. The algorithm should, as closely as possible, understand statements like:
The USB port must be 2mm from the left edge on the top side
The decoupling capacitors must be near the power pins on the microcontroller
The left and right headers must be spaced 20mm apart, and aligned
Copy the placement from the datasheet EXACTLY for this subcircuit
How do we capture these requirements? In tscircuit, they are captured through <group>/<subcircuit> tags with different layoutMode properties, also coordinate specifications like pcbLeftEdgeX=calc(board.minx + 2mm) . In some cases, the entire layout can be resolved by ordering the computations properly, but more often than not, this way of specification is arduous for the user and inflexible as a design grows.
For underspecified placements, Sequential Optimal Packing is a fast, deterministic and legible solution for packing. It allows us to capture “flexible” design constraints in a predictable way.
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