GoKawiilAegis
Aegis is a fully open-source FPGA, from the silicon up.
Existing open-source FPGA efforts either reverse-engineer proprietary architectures (Project IceStorm, Apicula) or build tooling around closed silicon (Yosys, nextpnr). The silicon itself has always been proprietary. Aegis starts at the other end: the fabric design is open, the toolchain is open, and the path to real silicon goes through open PDKs and shuttle services like wafer.space.
The project generates parameterized FPGA devices with LUT4, BRAM, DSP, SerDes, and clock management tiles, along with everything needed to synthesize user designs onto them and tape out the fabric itself to a foundry.
Devices
Aegis Terra 1
The first Aegis device, targeting GF180MCU via wafer.space.
Resource Count LUT4 ~2880 BRAM (128x8) 128 tiles DSP18 (18x18 MAC) 64 tiles I/O pads 224 SerDes 4 Clock tiles 2 (8 outputs) Routing tracks 4 per edge
nix build . # terra-1 # Generate IP (SV, JSON, chipdb, techmap) nix build . # terra-1-tapeout # Full RTL-to-GDS for fab submission
Toolchain
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