GoKawiilPCI Express (PCIe) is a foundational technology that's been around for decades, and that's not going to change anytime soon. The standard is set to change and evolve over the coming years, and the technology has a rich history behind it, too. PCIe inherited elements from the original PCI standard (such as configuration space, PnP, BARs, and command/status registers), so the history of this technology stretches into the annals of computing history.
Ever since its introduction in 2004, PCIe has been evolving in accordance with a simple rule: each new major revision roughly doubles link bandwidth while maintaining backward compatibility. The pace of formally introducing a new PCIe version every three or four years remained mostly stable, barring a major slip between PCIe 3.0 and PCIe 4.0. But what changed in recent years is not the pace, but the difficulty of each new iteration. Early generations increased throughput almost effortlessly by doubling transfer rates (clocks) and improving encoding efficiency. Today, the roadmap pushes PCIe directly into the territory where manufacturing tolerances, materials, and retimers define what is possible and how much it costs.
Nonetheless, PCI-SIG, the standard that oversees the development of PCIe and adjacent standards, continues to steadily introduce new PCIe generations every three to four years, ensuring its relevancy for years to come. Before diving into the future of the standard, let's first take a look back at history.
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A quick look back
PCIe began as a replacement for shared buses in the early 2000s and introduced point-to-point connections and scalable lane counts. PCIe 1.0 operated at a 2.5 GT/s data transfer rate per lane, followed by PCIe 2.0 at 5 GT/s. PCIe 3.0 increased the data rate to 8 GT/s, which was far from doubling the prior generation, but introduced a more efficient 128b/130b NRZ encoding scheme, which significantly reduced protocol overhead.
PCIe 4.0 doubled the transfer rate to 16 GT/s in 2017, and marked the first time where a new PCIe revision was adopted by enthusiast-grade desktop PCs only two years after the formal publication of the standard.
Swipe to scroll horizontally PCIe standards Revision Max Data Rate Encoding Signaling PCIe 7.0 (2025) 128.0 GT/s 1b/1b (Flit Mode*) PAM4 PCIe 6.0 (2022) 64.0 GT/s 1b/1b (Flit Mode*) PAM4 PCIe 5.0 (2019) 32.0 GT/s 128b/130b NRZ PCIe 4.0 (2017) 16.0 GT/s 128b/130b NRZ PCIe 3.0 (2010) 8.0 GT/s 128b/130b NRZ PCIe 2.0 (2007) 5.0 GT/s 8b/10b NRZ PCIe 1.0 (2003) 2.5 GT/s 8b/10b NRZ
PCIe 5.0 followed in 2019 at 32 GT/s per lane, and brought the electrical designs of data centers to client systems, requiring higher-grade PCB materials and stricter signal-integrity controls. Now, the bus provides up to 128 GB/s bidirectional bandwidth through an x16 slot, which is an overkill for consumer graphics cards, but increasingly useful for AI accelerators and high-end storage.
While PCIe 5.0 connectivity is must have for data centers, not every mainstream and entry-level consumer PC supports PCIe 5.0 for SSDs and graphics cards, which highlights that the cost of the technology introduced in 2019 is still fairly high for inexpensive computers.
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