GoKawiilIntel CFO Dave Zinsner told the Morgan Stanley TMT conference last month that Intel Foundry is "close to closing some deals that are in the billions per year in terms of revenue" on advanced packaging alone, with EMIB-T, the next-generation variant of Intel's embedded bridge technology, driving customer interest as TSMC's CoWoS-L capacity remains structurally oversubscribed.
That tech, EMIB-T, which adds through silicon vias (TSVs) to the bridge, is expected to enter production fab rollout this year and addresses the limitations that have kept standard EMIB out of high-power AI accelerator sockets: HBM 4 class power delivery and large package scaling.
If these “billions per year” in deals close, it’d mark quite the turnaround for Intel Foundry, which generated just $307 million in external revenue last year against a $10.3 billion operating loss. Given that 18A isn’t expected to reach industry-standard yields until next year at the earliest, packaging is the fastest on-ramp for Intel, and EMIB-T is what could convert that into AI accelerator revenue. Intel Foundry's most recent announcement aligns well with this, having signed up to join Musk's Terafab project, though the reality of the effort delivering on all that's been promised remains extremely optimistic, as we've broken down.
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EMIB-T and PSVs
(Image credit: Tom's Hardware)
Standard EMIB, which has been in volume production since 2017, embeds small silicon bridge dies in cavities within an organic substrate to route signals horizontally between adjacent chiplets, avoiding the cost and reticle limits of a full silicon interposer.
Intel deliberately skipped through-silicon vias entirely with EMIB, keeping the bridge die simple and cheap. That meant power had to be routed around the bridge via the organic substrate in long, resistive paths, limiting the current that could be delivered to the dies above. That ceiling was fine for the likes of Sapphire Rapids and Ponte Vecchio, but not for HBM4-class accelerators.
EMIB-T reverses that decision by adding through-silicon vias (TSVs) to the bridge die. In doing so, EMIB-T enables vertical power delivery directly through the bridge, integrates Metal-Insulator-Metal capacitors for noise suppression, and adds a copper ground plane grid for signal isolation.
Dr. Rahul Manepalli, Intel Fellow and VP of Substrate Packaging Development, gave us a look into the full specifications of EMIB-T at last May’s Electronic Components Technology Conference — a 45-micron bump pitch with a roadmap to 35- and 25-micron, energy efficiency of around 0.25 pJ/bit, and UCle-A interfaces running at 32 Gb/s of data transfer or higher per pin. EMIB-T supports HBM3, HBM3E, HBM4, and future HBM5 stacks, and scales to a 120mm x 180mm package supporting more than 38 bridges and over 12 reticle-sized dies.
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