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Enthusiast builds his own RAM in garden shed cleanroom — fledgling array of memory cells groundwork for much larger future project

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Why This Matters

This article highlights a groundbreaking DIY effort to manufacture RAM at home, showcasing the potential for individual innovation in addressing semiconductor shortages and industry challenges. It underscores the importance of accessible semiconductor manufacturing techniques amid rising demand and supply constraints, especially driven by AI and gaming industries.

Key Takeaways

Dr. Semiconductor is back in his shed, and this time he’s checking whether Joe Public can DIY themselves out of the DRAM crisis. In the video embedded below, you can see the good doctor go through the semiconductor process steps required to make an array of memory cells in a backyard shed cleanroom. This is the “first time ever RAM has been made at home,” boasts our hero.

Making RAM at Home - YouTube Watch On

RAMageddon isn’t the only issue affecting PC DIYers and the industry in general. Dr. Semiconductor mentions the AI-industry-fueled RAM price disruption being driven by the big three players (but there are others) not being able to keep up with demand. We are seeing similar effects on storage, GPUs, and some reckon CPU supplies will also begin to be impacted.

With the existing industry incapable of addressing consumer RAM needs at attractive prices in 2026, the TechTuber asks, “I turned a shed in my back yard into a class 100 semiconductor cleanroom… but the question is, can I make my own RAM?”

Article continues below

After the intro, Dr. Semiconductor gives a brief description of how computer memory works, and how it is largely made up of huge arrays featuring oodles of capacitors and transistors.

Moving on to the practicalities of the job at hand, the good doctor begins by snipping a couple of silicon chips from a large sheet. This is the beginning of the preparation and cleaning stage of the chipmaking process.

Next up, we move to the initial patterning stage. A layer of oxide is built on the surface of the silicon in a high-temperature furnace. It is estimated that this layer is 330nm thick. On top of this layer, an adhesive layer and photoresist film are applied. UV exposure projects a design mask onto this newly created surface, which allows a developer solution to wash away the areas that have been hit by the light rays.

The source and drain of the transistors in the design are formed in the following steps. This involves more layer etching, doping exposed silicon to make it highly conductive, then annealing the chips to push the doping agent deeper.

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