GoKawiilNEO Semiconductor announced on April 23rd that its 3D X-DRAM technology has successfully passed proof-of-concept (POC) validation, demonstrating that a new class of high-density DRAM can be manufactured using existing 3D NAND infrastructure. The company simultaneously announced a new strategic investment led by Stan Shih, founder and former Chairman and CEO of Acer, and a board director of TSMC for over two decades.
At the center of the announcement is the company’s 3D X-DRAM technology, a new class of DRAM that aims to break past conventional memory scaling limits by adopting a vertically stacked architecture designed for higher density, lower power consumption, and improved suitability for AI-driven workloads.
NEO’s 3D X-DRAM’s architecture draws heavily on 3D NAND manufacturing techniques. According to the company, the POC chips were produced using mature 3D NAND processes, including existing equipment and materials. This is a critical point, as one of the main constraints in advanced memory development is not design innovation, but fabrication cost and process compatibility.
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The proof-of-concept chips, fabricated and tested at Taiwan's National Institutes of Applied Research - Taiwan Semiconductor Research Institute (NIAR-TSRI) in collaboration with National Yang Ming Chiao Tung University, delivered the following results:
Read/write latency: under 10 nanoseconds
Data retention: over 1 second at 85°C/185°F (claimed 15× improvement over JEDEC standard)
Bit-line disturbance: over 1 second at 85°C (185°F)
Word-line disturbance: over 1 second at 85°C
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