GoKawiilAI chip design startup Verkor.io claims, in a research paper published in March, that its agentic AI system, Design Conductor, autonomously produced a complete RISC-V CPU core — taking a 219-word requirements document and generating a verified, layout-ready design in 12 hours, which is orders of magnitude faster than the standard 18- to 36-month timelines seen in commercial chip design.
This is the first time an autonomous agent has built a working CPU from spec to GDSII layout file, according to Verkor. The resulting processor — VerCore — is a five-stage pipelined, in-order, single-issue core that met timing at 1.48 GHz on the ASAP7 7nm process design kit, scoring 3,261 on the CoreMark benchmark.
Verkor’s paper goes into detail on the pipeline architecture, which includes instruction fetch, decode, execute, memory, and writeback stages with early branch resolution and operand forwarding.
During optimization, the system independently implemented a fast Booth-Wallace multiplier that clocked at 2.57 GHz and a one-cycle branch penalty design that the agent selected after implementing and testing both one-cycle and two-cycle variants. Verkor compares VerCore's CoreMark performance to Intel's Celeron SU2300, a 2011 mobile chip based on the Penryn architecture.
A five-stage in-order core with no caches and no out-of-order execution is a fairly straightforward design by industry standards. Verkor's own paper notes that leading-edge chips cost north of $400 million and take 18 to 36 months with engineering teams in the hundreds, but VerCore is far simpler than those designs. That said, the 12-hour timeline is still notable for a fully autonomous run from spec to layout, even if it did require "many tens of billions of tokens" at this comparatively pale level of complexity.
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(Image credit: Verkor.io)
VerCore hasn’t been physically fabricated and was instead verified in simulation using Spike, a reference RISC-V ISA simulator, and ASAP7 is an academic process design kit, not a production 7nm node. Verkor says it can run a uCLinux variant in simulation.
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