GoKawiilA Field Guide · 2026 Co-Packaged Optics Supply Chain An interactive map of the package architecture replacing pluggable optical transceivers in next-generation AI and HPC switches.
What is co-packaged optics (CPO)? Co-packaged optics integrates the optical engine — InP laser, silicon photonics chiplet, modulators, and photodetectors — directly into the same package as the switch ASIC or AI accelerator. By eliminating the long electrical traces between a front-panel pluggable transceiver and the switch silicon, CPO reaches 1.6T–6.4T per port at a fraction of the power per bit. As AI accelerator fabrics scale beyond a single rack, CPO becomes the gating technology for optical I/O.
The four package layers InP laser die — gallium-indium-phosphide chips that emit continuous-wave or modulated light. Built on InP epitaxial wafers with MOCVD-grown active layers. Hybrid bond interface — direct copper-to-copper and oxide-to-oxide bonding that fuses the InP die to the silicon photonics chiplet at sub-micron alignment. Silicon photonics (SiPh) chiplet — passive and active waveguides, ring modulators, grating couplers, and germanium photodetectors patterned in CMOS-grade silicon-on-insulator. Switch ASIC or accelerator — the digital silicon (Broadcom Tomahawk, NVIDIA Spectrum-X / Quantum-X, custom hyperscaler XPUs) that sits inches from the optics through advanced packaging.
Supply-chain chokepoints SOITEC — engineered SOI wafers; functionally no second-source for the SiPh substrate.
— engineered SOI wafers; functionally no second-source for the SiPh substrate. ASML — EUV lithography for the leading-edge switch ASIC; sole supplier worldwide.
— EUV lithography for the leading-edge switch ASIC; sole supplier worldwide. Sumitomo Electric and IQE — InP epitaxial wafers; a duopoly with multi-quarter lead times.
— InP epitaxial wafers; a duopoly with multi-quarter lead times. EV Group — wafer-to-wafer hybrid bonders; the rate-limiting step at the laser-to-SiPh interface.
— wafer-to-wafer hybrid bonders; the rate-limiting step at the laser-to-SiPh interface. TSMC — CoWoS-S and CoWoS-L advanced packaging for the assembled CPO stack.
— CoWoS-S and CoWoS-L advanced packaging for the assembled CPO stack. Lumentum, Coherent, Sivers Photonics — vertically integrated InP and merchant CW/EML laser sources; Sivers is a strategically important non-Asian, non-US foundry.
— vertically integrated InP and merchant CW/EML laser sources; Sivers is a strategically important non-Asian, non-US foundry. Shin-Etsu and SUMCO — 12-inch silicon wafers feeding the SiPh chiplet.
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