GoKawiilResearchers led by Illinois Grainger Engineering professor Qing Cao have demonstrated a scalable way to directly and sequentially stack high-performance silicon circuits. This advance marks a critical step toward realizing the full potential of three-dimensional chips that could carry computing beyond the limits of traditional scaling.
For more than half a century, the power of computers has grown by shrinking transistors and packing them more tightly onto flat chips. It worked too well. Devices are now becoming so small that they start to be fundamentally limited by atomic dimensions and quantum effects.
The next leap can come from adding a new dimension: building upward. By vertically stacking layers of silicon circuits, chipmakers can dramatically increase computing density and speed while reducing energy use, offering a promising route to extend Moore’s law without shrinking transistors any further.
“Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. ” Associate Professor Qing Cao, Department of Materials Science and Enginering
Illinois Grainger Engineering materials science and engineering professor Qing Cao explains, “Take something as simple as static random-access memory, which is universal in CPUs and GPUs. Today it takes six microelectronic devices called transistors on a single plane to store one bit of information. With vertical integration, you can distribute them across multiple layers. It’s like replacing a sprawling suburb with high-rises: you get the same functionality, but the spatial footprint is reduced while making communication between layers faster and more efficient.”
The most efficient approach, known as monolithic three-dimensional integration, builds each layer directly on top of the previous one to maximize interlayer connectivity. However, achieving this has been a longstanding technical challenge. Preparing high-quality silicon and fabricating high-performance devices normally require processes operating at 1,000 degrees Celsius, hot enough to destroy the metal wiring. For upper layers beyond the first, the temperature constraint, or “thermal budget,” is strictly set to 400 degrees.
A freestanding sheet of single‑crystalline silicon nanomembrane is held above a silicon wafer patterned with its first layer of electronic circuits.
A team of Illinois Grainger Engineering researchers led by Cao has now shown that it is possible to stay within that limit while still achieving high device performance across multiple tiers. Their newly invented process uses single-crystalline silicon — the main semiconductor used in industry — and has demonstrated device yields of 98‒100%, even in an academic laboratory cleanroom setting, indicating strong potential for industrial adoption.
“Vertical integration is already starting to make its way into commercial devices, particularly in specialized AI hardware, but monolithic integration is what unlocks the full promise of 3D chips,” Cao said. “For the first time, we have met the thermal budget of monolithic 3D integration using standard single-crystalline silicon and delivered unprecedented performance.”
This study appears in Nature as one of the journal’s rare research articles focused on silicon microelectronics.
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