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8086 Segmented Memory was a good idea

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Why This Matters

This article highlights the innovative yet complex design of the 8086's segmented memory architecture, which initially aimed to expand addressable memory but ultimately became a source of developer frustration. Understanding this historical design sheds light on the evolution of memory management in modern processors and the importance of balancing technical ingenuity with usability. It underscores how software development challenges can influence hardware design decisions and their long-term impact on the industry and consumers.

Key Takeaways

How’s that for a click‑bait title. Who in their right mind would defend the monstrosity that is the 8086 segmented memory architecture?

By the time I got into 8086 assembly, PCs were mostly 80286‑based, but everything still ran under DOS. A “normal” machine only had the canonical 640KB of conventional memory and every assembly book had a dreaded chapter explaining segmentation. I still have the battle scars. Near pointers, far pointers, and the infamous “wherever‑you‑are” pointers.

So when I found myself making similar architectural decisions for Hearthfire, my project to design a hypothetical 1980s‑era home computer with the benefit of hindsight and without the burden of actually manufacturing silicon, I finally understood why Intel made the choices they did. Segmentation could have been a solid foundation for the future except for one small detail that ruined everything.

And that detail, awkwardly, was us.

Software developers.

We broke it.

“There are many things that I would like to say to you but I don’t know how.”

What Is 8086 Segmented Memory?

The 8086 could address 1MB of memory which was a huge amount when 64KB was considered luxurious. To do that, it needed 20‑bit addresses.

But instead of giving programmers 20‑bit registers, Intel kept the familiar 16‑bit registers and the missing four bits came from a second set of 16‑bit registers called segment registers. Each memory access combined one of these segment register and a 16‑bit offset.

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