GoKawiil“It’s not just an incremental step,” Jay Gambetta, the director of IBM Research, said during a press conference on Tuesday. “It’s a meaningful leap forward.” Within a decade, Gambetta expects, chips with nanostacking will be widely used in data centers, where their improved efficiency could help the facilities better manage their energy consumption.
“Absolutely, it’s transformational,” says Dan Hutcheson, vice chair of TechInsights, a technology analysis company. “This puts another 10, 15 years on the roadmap.”
Compared with IBM’s previous state-of-the-art architecture, the company reports, chips built with this new approach can do as much as 50% more work in the same amount of time and be up to 70% more energy efficient.
The architecture offers a general way of laying out transistors, and IBM will partner with semiconductor manufacturers to make the actual chips. It anticipates that chip designers will deploy the design in many different types of chips, including GPUs and CPUs. “I expect to have many conversations with designers about how they can use this technology,” Huiming Bu, IBM’s vice president of global semiconductor R&D, said in the press conference announcing the new design.
A layer cake
Engineers created IBM’s new chip layer by layer, like a cake. They start by fabricating transistors on one layer of silicon. Then they place a silicon layer on top of these devices, and they fabricate another layer of transistors directly on top of that. Finally, they create the electrical connections between the two layers of transistors. This kind of vertical stack, which combines two types of transistors, is known as a complementary field-effect transistor, or CFET, explains Qing Cao, a professor of materials science and engineering at the University of Illinois at Urbana-Champaign, who was not involved with the work.
The company isn’t the only one pursuing this general approach. The biggest chip manufacturers—Intel, Samsung, and TSMC—and the competing research lab Imec in Belgium have been investigating CFETs. IBM says its design is distinguished by the fact that the transistors in the second layer do not sit directly on top of the first layer’s transistors; rather, they are staggered, which the company says simplifies wiring, among other advantages.
CFETs like those in IBM’s nanostack architecture contrast with another common approach to making two-tiered chips, such as AMD’s 3D V-Cache and Huawei’s forthcoming LogicFolding technology, Cao says. In those approaches, engineers fabricate the transistors on each layer of the chip independently before bonding the two together. IBM’s new method allows for more precise alignment of the layers, which is important for performance because transistors are so tiny, says Cao.