GoKawiilIBM on Thursday said it has produced the first test chip using its 0.7nm-class (7 angstroms) fabrication technology, the industry's first sub-1nm manufacturing process. The concept process technology relies on the so-called nanostack transistors and promises rather dramatic power, performance, and area (PPA) gains compared to IBM's 2nm-class node. To produce nanostack transistors, IBM uses two wafers instead of one, along with ultra-thin dielectric bonding, an arrangement that has never been used before.
IBM's 7A-class (or 0.7nm-class) fabrication process based on nanostack transistors is said to offer up to 50% higher performance and 70% higher energy efficiency compared to IBM's 2nm-class node based on nanosheet gate-all-around transistors the company introduced in 2021. Perhaps more importantly, IBM's nanosheet architecture provides a 40% higher SRAM density and even higher density improvements for logic transistors, gains that are extremely hard to achieve these days.
Such massive gains have been enabled by numerous innovations, but the key enabler is IBM's nanostack transistor architecture, which conceptually resembles CFETs and stems from GAA nanosheet transistors.
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Two wafers instead of one
In modern process technologies, all logic transistors live in one active device tier, and NFETs and PFETs sit side by side laterally in the standard-cell layout. Nanosheet GAA transistors feature a more advanced internal geometry, but they still reside in this single-transistor tier, which gets harder to shrink with every generation.
(Image credit: IBM)
IBM's nanostack concept seems to separate complementary n-type and p-type transistors into vertically bonded tiers instead of placing them side by side in a single transistor layer. The payoff is a major reduction in the lateral footprint of a CMOS pair, as the architecture effectively turns one NFET+PFET structure from a 2D layout into a 3D stacked layout, which is why IBM can claim roughly double transistor density versus its 2nm research node without relying on conventional planar shrink.
While conceptually IBM's nanostack transistors resemble CFETs, the way IBM builds its nanostacks is fundamentally different compared to monolithic CFETs proposed by various chipmakers and organizations. N-type and p-type transistors are fundamentally the same kind of transistor used as complementary partners in CMOS logic, but they differ in carrier type (electrons for n-type and electron holes for p-type), switching polarity, and electrical behavior, which is why advanced process technologies tend to optimize them separately. However, these n-type and p-type transistors are made on the same wafer using essentially the same materials, so the level of their optimization is limited today.
(Image credit: IBM)
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