GoKawiilIn response to the increasing needs of artificial intelligence computations and rising requirements in data centres and mobile devices, the necessity to fabricate transistors that are high-density, high-performance and energy-efficient has become increasingly urgent. For decades, the scaling of silicon has adhered to Moore’s law, yet it now approaches a challenging phase as it nears the physical limits of Si. Among the option for post-Si channel materials, two-dimensional (2D) materials emerge as the cornerstone for the continuing scaling of transistors2, offering potential advantages in low-power consumption. This miniaturization primarily depends on the scaling of channels and contacts, which involves not only shortening the channel length but also scaling down the size of metal contacts, the crucial gateways for current injection. This presents a marked challenge because shrinking their size can often lead to performance-limiting contact resistance. Substantial efforts have been made in understanding the scaling limitation for ultrathin 2D materials, in particular, on the channel scaling of monolayer (ML) 2D materials for the transistors beyond 1 nm technology node3,4. However, the equally important metal contact scaling has received very little attention, and it presents a tough challenge, especially for 2D material-based field-effect transistors (FETs), because their current crowding is expected to be prominent at the nanoscale contacts. Numerous research groups have ventured into modifying contact materials or adopting interface engineering techniques to mitigate the high contact resistance issue6,7,8,9,10,11,12. However, the task of contact size reduction is still mostly unexplored. One of the inherent challenges lies in the determination of transfer length (L T ), which is the effective current injection region between metal contact and 2D material, and it corresponds to the limitation of contact size scaling. A previous study13 used ab initio simulation to demonstrate that the electron injection from a top metallic contact into underlying 2D material can occur either at the edge or the overlap area of metal/2D materials interface, depending on the interface properties, implying that the carrier transport strongly relies on contact metals, 2D channel materials and thicknesses, and metal/2D interface quality. Furthermore, precise and controllable fabrication of sub-20-nm contacts is still very challenging, which makes it more difficult to determine the contact size limit experimentally.
Early studies have made notable strides in this area. A previous study14 used an ultrahigh-vacuum metal deposition method to fabricate few-layer MoS 2 transistors with an Au contact, estimating a transfer length of around 35 nm. Another study15 demonstrated that Ni contacts on few-layer MoS 2 transistors, fabricated using e-beam lithography, maintained on-state current even with a contact length of 13 nm, suggesting an L T ≤ 13 nm for Ni and few-layer MoS 2 . MoS 2 FETs with Au/Ni contact lengths varying from 300 nm to 20 nm on ML 2D FETs were fabricated in ref. 8, indicating a transfer length of approximately 45 nm. Recently, another study16 has shown that semimetal antimony (Sb) as a contact metal in ML-MoS 2 transistors can maintain on-state current even with a 30 nm contact length. Extrapolating through TCAD (technology computer-aided design) model simulation, the study predicted a contact length scaling for Sb-MoS 2 at approximately 15 nm. Various reported values of L T estimation for MoS 2 are summarized in Extended Data Table 1. Despite these advancements, all the transfer length estimation still relies on theoretical simulation or extrapolation of a series of devices with varied metal sizes through theoretical models7,17,18,19, where many assumptions are unavoidable to approximate the transfer length. Until now, there is still a lack of direct measurement for the nano-scaled transfer length at the 2D/metal interfaces in a transistor device, that is urgently needed to understand the scaling constraints for advanced electronics.
Here, we use cross-sectional scanning tunnelling microscopy and spectroscopy (XSTM/S), with the ability to probe electronic structures on a sub-nanometre scale while applying an in situ operating voltage between source and drain, to measure the current injection length in metal–2D contact. As a semimetal such as bismuth (Bi) or Sb has been demonstrated as almost barrier-free and exhibits extremely low contact resistance on MoS 2 , with great potential to reach the ultra-scaled contact size6,9,11, Bi-contacted ML-MoS 2 is selected in the study to understand the limit of contact scaling. Note that compared with 2D few layers, the ML is considered more suitable for advanced scaling owing to its ultimately thin thickness for desired gate controllability. With this, we have made the direct nanometre-scale experimental measurements of the current injection length of 2D ML transistors. Our findings show a current injection length of approximately 2.0–3.0 nm for Bi on ML-MoS 2 transistor at room temperature, meeting the metal width requirement in the 1 nm technology node1 (<18 nm). We anticipate that this proposed metrology will serve as a stepping stone for further experimental endeavours in contact engineering, nanoscale device physics and advanced electronics.
To validate the good electrical contact between chemical vapour deposition (CVD)-grown MoS 2 (see the Methods for the growth) and Bi, back-gated MoS 2 FETs with varying channel lengths were fabricated, and the transfer length method (TLM) was used for characterizing contact resistance. The optical image and schematic of the measured MoS 2 device are shown in Fig. 1a. The flowchart of MoS 2 device fabrication with SiO 2 (100 nm) as the gate dielectric is shown in Extended Data Fig. 1 and can be referred to in previous publications20,21. Figure 1b shows the output characteristics, source–drain current (I DS ) and source–drain voltage (V DS ) as a function of gate voltage (V GS ) in one of the measured MoS 2 FETs, where the measured I DS exhibits a linear dependence on the V SD . The α value, derived using the power law I DS = V DS α, is estimated to be approximately 1.00, as shown in Fig. 1b (inset), confirming an ohmic-like contact behaviour5. Figure 1c shows the transfer curves (I DS –V GS ) as a function of V DS in the identical device, exhibiting moderate on-current density and standard n-channel conducting behaviour with an on/off current ratio of larger than 106 at V DS = 1 V and within the V GS range of ±40 V, as shown in Fig. 1c (inset). To estimate the contact resistance (R c ) in our MoS 2 FETs, R c is extracted from the relationship between total resistance (2R c ) and channel lengths at a consistent gate voltage, as shown in Fig. 1d. The value of R c is determined by half of the y-axis intercept resulting from a linear fit to the data points. Consequently, the R c for a Bi contact to ML-MoS 2 is as low as about 70 Ω μm at a carrier concentration of 6.8 × 1012 cm−2. The carrier concentration induced by electrostatic gating is estimated by assuming a simple linear charge dependence on the gate voltage. The corresponding I DS –V DS curves for the determination of contact resistance are provided in Extended Data Fig. 2. Figure 1d (inset) shows not only the total contact resistance but also transfer length (2L T ), determined using the extrapolation method from the TLM. The minimum L T obtained is approximately 9.25 nm. The gate dependence of R c and L T extracted from the TLM is summarized in Supplementary Table 1, which shows that L T increases with increasing gate voltage (that is, higher carrier concentration). The L T values from the TLM will be compared with those derived from the XSTM measurement later.
Fig. 1: ML-MoS 2 FET and its electrical characteristics. Full size image a, Optical image (top) and schematic (bottom) of one selected MoS 2 device for the TLM. b, Typical I DS –V DS curves as a function of V GS . The inset is the double-logarithmic I DS −V DS plot, in which the power law of α is about 1.00, indicating an ohmic-like behaviour in the Bi-contacted MoS 2 FETs. c, Typical I DS –V GS curves as a function of V DS . The inset is the logarithmic I DS –V GS plot, in which the on/off ratio is larger than six orders of magnitude. d, Correlation between the measured total resistance and the channel length measured for the TLM devices on SiO 2 (100 nm)/Si substrate. The inset shows a contact resistance (R c ) of about 70 Ω μm and the transfer length (L T ) by the extrapolation method. Scale bar, 2 μm (a).
In this work, a Bi-contacted ML-MoS 2 transistor with a channel length of 2 μm is prepared for XSTM measurements. We design a device based on the CVD MoS 2 ML contacted with two-terminal Bi source and drain metals, in which the main part of the device fabrication is shown in Fig. 2a. To directly probe the length of carrier injection at the contact edge of Bi-contacted MoS 2 transistors, we develop device-operating XSTM in this work, in which the ML-MoS 2 transistor with Bi contacts is cleaved with mechanical force in an ultrahigh-vacuum chamber (Fig. 2b). This methodology avoids environmental contamination and molecular absorption that may affect the characterization of their electronic structures (for details, see Supplementary Note 1). Meanwhile, it also provides the ability to directly measure the electronic structure at heterointerfaces. Furthermore, to investigate the carrier transport behaviour under operating conditions, we successively applied the V DS on the cleaved transistor in an ultrahigh-vacuum chamber (Fig. 2c) to generate a current from the drain to the source contact, while applying the V G between the source and the gate (Si substrate). For device performance of the transistor for XSTM measurement, refer to Supplementary Note 2. We conduct the operando XSTM spectroscopy measurement at the ML-MoS 2 at underlying the Bi drain contact and at the channel region to investigate the spatially resolved local electronic structure of MoS 2 with and without applying V DS . Figure 2d schematically shows the cross-sectional structure of the Bi drain contact with MoS 2 , in which we define the physical edge of Bi metal towards the channel side as the contact edge (C.E.). Figure 2e,f shows the cross-sectional STM topography of the Bi-contacted MoS 2 transistor around the C.E. Furthermore, the position of the ML-MoS 2 film was delineated using the density-of-states mapping in XSTM spectroscopic measurements (Fig. 2g). This identification is also consistent with separate cross-sectional scanning transmission electron microscopy (STEM) and energy-dispersive X-ray spectroscopy measurements (Fig. 2h).
Fig. 2: Schematics and XSTM measurements across the Bi/MoS 2 interface. Full size image a, Schematic of the sample structure. b, Cross-sectional STM sample cleaved in ultrahigh vacuum. The channel length and the contact length of the sample device are 2 µm. c, XSTM probing on the cross-sectional side of the sample, in which a source–drain bias V DS is applied during the STM measurement, with V S denoting the sample bias for the STM process. d, Schematic of the device structure close to the Bi drain contact and MoS 2 . The edge of the Bi drain contact is labelled as C.E. (contact edge). e, Large-area topography image showing the overall cleaved surface at the C.E. region, from the Bi contact, across the HfO 2 dielectric, to the Si substrate. f, High-resolution topography image focused on the C.E. region with first derivative computation for each line in the x-axis to extract the contours of the Bi contact and MoS 2 ML (black lines) at the C.E. region. g, High-resolution dI/dV image with the same Bi contour at the C.E. determined in f, image acquired at sample bias V s = +2.0 V, current I t = 400 pA and source–drain voltage V DS = 0.0 V. The white and red dashed lines in f and g represent the position of the STS line scans, as detailed in Supplementary Note 3. h, HR-XTEM image of Bi/MoS 2 interface (top) and the corresponding EDX element mapping (bottom). a.u., arbitrary units. Scale bars, 50 nm (e); 5 nm (f,g); 20 nm (h, top and bottom).
Large-range XSTM scanning was used in the experiment to locate the ML-MoS from the substrate to the top surface of the sample. Once the ML-MoS 2 was found, the direction of scanning measurement was switched to investigate along the direction parallel to the MoS 2 film until the Bi-MoS 2 C.E. was crossed over. For details of locating and identifying the MoS 2 layer and C.E., refer to Supplementary Notes 3 and 4. Then, we spatially scan through the MoS 2 to the C.E. and the channel after magnifying the scanning region to the MoS 2 under the Bi contact metal. Leveraging the inherent high resolution of STM, we can conduct the scanning tunnelling spectroscopy (STS) measurement at a specific distance from Bi to the bottom Si and distinctly identify the STS curves of MoS 2 with high spatial resolution (Fig. 3a). The STS data for Si show the bandgap measured at approximately 1.1 eV, consistent with existing studies22. For MoS 2 , the observed bandgap was approximately 2.3 eV (ref. 23). Bi shows a non-zero slope at zero voltage, indicating its metallic properties, whereas the SiO 2 between Si and MoS 2 shows a wide bandgap character, which is consistent with its dielectric role.
Fig. 3: Cross-sectional STS measurements and band edge evolution in MoS 2 devices with different operating conditions and under different regions. Full size image a, The STS evolution from Bi (green) to MoS 2 (yellow) to SiO 2 (brown) with 0.4 nm resolution at V DS = 0.0 V with 0.4 nm resolution. We select the MoS 2 curve close to the oxide at each point for further STS analysis. b, Comparison of tunnelling spectra for MoS 2 under Bi Drain at different distances (C.E., A, B to H correspond to 0–6.4 nm at a 0.8 nm interval) away from the C.E. with varying V DS (0 V and 0.5 V). The dI/dV curves are plotted in logarithmic scale. The dotted lines indicate the position of the conduction band edge (E C ). See Supplementary Notes 9 and 13 for the counterpart figures to a and b for the device with HfO 2 as the dielectric layer. For the definition of the x-axis of STS data, \(E-{{E}_{\text{F}}}^{{\text{MoS}}_{2}}\), refer to Supplementary Note 14. c,d, Comparison of conduction band edges E C under Bi source (c) and drain contacts (d) for MoS 2 devices with SiO 2 as gate dielectric under varying V DS . The zero position of the x-axis corresponds to the C.E. e,f, Gate-voltage dependence of the conduction band edge E C in the Bi/MoS 2 /SiO 2 device at fixed V DS = −0.5 V, measured near the source (e) and drain contacts (f). The measurements were performed at three different gate voltages (V G = 0 V, 0.5 V and 2.0 V). For details of uncertainty calculation, refer to Supplementary Note 7. a.u., arbitrary units.
To systematically probe the carrier transport behaviour, we performed operando STS line scans to extract dI/dV curves of MoS 2 from the region under contact to the channel with two different gate dielectrics (20 nm HfO 2 and 100 nm SiO 2 ) under varying V G and V DS applied in situ. For performance comparison of devices with HfO 2 and SiO 2 as dielectric layers, refer to Supplementary Note 5. For details of optimizing spatial resolution and sampling strategy for the operando measurement, refer to Supplementary Note 3. The device with 100 nm SiO 2 enables comprehensive investigation of both V DS and V G while minimizing gate leakage. The measured conduction band (CB) edge energy evolves with the location as shown in Fig. 3b. To understand the detailed evolution of band structure, we first focus on analysing the energy-band shifts along the CB edge at the drain area using the device with a 100 nm SiO 2 dielectric layer at V G = 0 V. The spatially resolved dI/dV spectra were collected at 0.8 nm intervals from the C.E. to 6.4 nm into the under-contact region. At V DS = 0 V, the MoS 2 CB edge maintains a consistent value of (0.82 ± 0.02) eV across all positions, as indicated by the yellow dotted line in Fig. 3b. On applying V DS = 0.5 V, we observe systematic shifts in all spectral curves, prompting a detailed analysis of the CB edge positions under different bias conditions, as presented in Fig. 3c,d. Note that the CB edge is extracted with the assumption that a linear region is observed on either side of the onset in the STS curve, as detailed in previous publications24 and Supplementary Note 6. The error bars of CB values and difference are calculated by including the uncertainties from each CB measurement and using error propagation25 to ensure a proper representation of the combined uncertainty (for details, see Supplementary Note 7). The position-dependent CB edge values measured on devices with both dielectric configurations reveal several key features. For the SiO 2 -based device, at V DS = 0 V, the CB maintains a uniform energy level throughout the measured region. On applying V DS = −0.5 V, we observe that the CB edge of MoS 2 exhibits a position-dependent shift under the drain contact. This shift extends into the channel region, where the CB edge difference between two measured points (about 3 nm from the drain and about 3 nm from the source) is (0.45 ± 0.11) eV, primarily reflecting the channel voltage drop, given that contact resistance accounts for less than 1% of the total resistance (Fig. 1).
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