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AMD’s Venice-X CPU launches in 2027 with 1152 MB of 3D V-Cache, 96 cores, and 5.15 GHz boost clock – Zen 6 CPU for high-performance computing comes with major pillars of Venice

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Why This Matters

AMD's Venice-X CPU, launching in 2027, represents a significant leap in high-performance computing with its 96 cores, up to 5.15 GHz clock speed, and an unprecedented 1152 MB of 3D V-Cache. This development highlights AMD's focus on maximizing cache and memory bandwidth for data center and HPC workloads, pushing the boundaries of CPU performance and efficiency. The chip's advanced features will likely influence future server architectures and accelerate AI and scientific computing applications.

Key Takeaways

AMD’s Venice-X CPU is launching in the second half of 2027, the company revealed Thursday at its Advancing AI event. The CPU is built on the same Zen 6 microarchitecture as Venice SP7, which AMD says is now in production, but it comes with smaller core counts and leverages AMD’s 3D V-Cache to stack an unbelievable 1152 MB of L3 cache on the chip, all while offering 96 cores and clock speeds up to 5.15 GHz.

We’ve previously heard teases of Venice-X, and AMD has released variants of its Epyc chips like this in the past, such as Milan-X and Genoa-X. But we never saw Turin-X, and we haven’t gotten any concrete details about Venice-X up to this point. Now, we have a peek into what Venice-X will offer, which looks similar to Genoa-X in some regards.

AMD is sticking with 96 cores with Venice-X, as well as 1152 MB of stacked L3 cache. There are a few major differences compared to Genoa-X , however. First, AMD says clocks are much higher here, claiming Venice-X tops out at 5.15 GHz (the 96-core Epyc 9684X clocks up to 3.7 GHz). Venice-X also comes with the memory improvements available in most of the chips in the range.

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It supports 16-channel memory, either with standard DDR5 RDIMMs at up to 8,000 MT/s or with new MRDIMMs 12,800 MT/s, offering up to 1.6 TB/s of aggregate memory bandwidth. The memory system in Venice broadly is a massive increase over Turin, nearly tripling the aggregate bandwidth, mainly on the back of speeds enabled by MRDIMMs.

Venice-X is one of four variations of AMD’s Zen 6 lineup for data centers, mainly targeting HPC workloads, with its massive L3 cache and relatively high clock speeds. Venice-X uses the same SP7 socket as the main Venice range. Other variations of Zen 6 offerings, including Verano, will use the SP8 socket instead.

AMD’s standard Venice chips support up to 1024 MB of L3 cache on their own, nearly triple that of its previous flagship offering. That cache is split among 256 cores, however. Venice-X doesn’t come with much more cache overall, but that cache is serving far fewer, more powerful cores, which should be useful in HPC workloads.

AMD didn’t disclose any other details about Venice-X, nor any performance projections. Given that it’s set to launch in the second half of 2027, we’re still a ways out from that.

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