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Weight-four parity checks in a spin-shuttling architecture

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Why This Matters

This research advances quantum computing by demonstrating weight-four parity checks within a spin-shuttling architecture, leveraging high-quality silicon-based qubits. The development of such error-correcting protocols is crucial for scalable, fault-tolerant quantum systems, directly impacting the future of quantum hardware and algorithms for both industry and consumers.

Key Takeaways

Device fabrication

The device is fabricated on an isotopically purified 28Si/SiGe heterostructure containing a 7-nm-thick strained quantum well19, 30-nm SiGe buffer passivated with an amorphous silicon cap, and a 10-nm atomic layer deposition of insulating Al 2 O 3 . The heterostructure is nominally equal to that in previous studies where large average valley splitting in excess of 200 μeV (ref. 19) and high-fidelity shuttling5 have been observed. The four proceeding Ti:Pd layers have thicknesses of 3:17 nm, 3:27 nm, 3:27 nm and 3:27 nm respectively and are each followed by 5-nm atomic layer deposition of Al 2 O 3 . Finally, a 3:150 nm Ti:Co micromagnet is evaporated. The gate layer order is selected (refer to Fig. 1a) to maximize the tunnel coupling tunability for two-qubit interactions between the ancilla and data qubits as well as the interaction between the PSB pair, as gates in higher layers typically exhibit lower lever arms to the buried quantum well51.

Experimental set-up

The experiments were performed in an Oxford Instruments ProteoxMX dilution refrigerator where the mixing chamber temperature was held at 200 mK to mitigate heating effects52. A driven superconducting vector magnet was used to magnetize the on-chip micromagnet in a field of 1 T and is otherwise unpowered. The device was glued with GE varnish to a copper plate in direct thermal contact with the mixing chamber and was wirebonded to an in-house printed circuit board (PCB). We applied DC bias voltages supplied by battery-powered home-built voltage source modules (D5a) and generated baseband control and readout pulses with a Qblox Cluster equipped with eight 4-channel QCM arbitrary waveform generator (AWG) modules and a QRM module for RF reflectometry readout. DC channels were filtered with a combination of PI and RC filters with a nominal cut-off frequency of about 20 Hz. Alternating current (AC) channels were filtered by ferrite chokes, passed through UT85 stainless steel semi-rigid coaxial cables and attenuated by 20 dB at 4 K to balance thermalization and have a large dynamic range for baseband pulsing. The ±2.5 V output range of the AWG channels corresponded to a ±500 mV available range at the device. The DC and AC signals were combined through bias tees with a time constant of 100 ms. Two channels of a QCM module are used for IQ modulation of a Rohde & Schwarz SGS100A vector source. We set the local oscillator of the vector source to 2.27 GHz to ensure that all target qubit frequencies fall on the same sideband within the 400-MHz bandwidth of the QCM. The output power of the vector source was set to 6 dBm.

The RF tone for readout was generated by the QRM, attenuated by 40 dB at room temperature and 20 dB at 4 K, and the input and output signals passed through a MiniCircuits ZEDC-15-2B directional coupler at the mixing chamber stage. The input power was set to optimize the signal-to-noise ratio of charge sensing. The output signal was carried through a superconduting NbTi UT85 cable to a Cosmic Microwave Technologies CMT-BA1 cryogenic amplifier mounted at the 4 K stage, which provides approximately 30 dB of amplification. The signal was further amplified at room temperature with a home-built amplifier (standalone M2j), which provided an additional 45 dB of amplification before being filtered, digitized and demodulated by the QRM. The demodulated signal was digitally rotated to the in-phase component to make use of real-time feedback.

Initial device testing and tuning procedure

After cooling below 1 K, RF reflectometry was verified by finding the LC circuit resonances with a spectrum analyser. We then proceeded to verify DC transport through both SET structures as well as the conveyor channel. This is shown for the latter in Supplementary Fig. 4. Although the adjacent bus-stop gates cannot pinch off the channel entirely, their large effect on the conducted current is an indication that they operate normally, as shown in Supplementary Fig. 5. After verifying DC transport, we benefited from a complete thermal cycle to reset hysteresis before tuning up sensors with RF reflectometry.

The pinch-off voltages within the channel provide a first guideline for DC voltages that allow the device to be accessible by shuttling. We find that the channel gates in the same layer pinch off with reasonable uniformity around 1 V. To avoid unwanted static charge accumulation under the conveyor, we therefore set their preliminary DC voltages in the range of 700–800 mV. As the DC tests on the bus-stop gates do not provide such a quantitative guideline, we rely on electrostatic simulations to estimate the bus-stop gate voltages needed to create a balanced double-dot potential with the corresponding conveyor gate. We extract roughly a factor 1.5 and 1 for the bus-stop plunger and barrier, respectively, compared with the conveyor gate voltages. We therefore set the bus-stop plungers to 1,200 mV and the bus-stop barriers to 750 mV as a reasonable starting point to tune the array.

After verifying DC functionality, the device tune-up proceeds in the following sequence: (1) ancilla readout and control, (2) coarse conveyor-mode shuttling, (3) single-spin remote tuning and virtual gate matrix calibration, (4) spin reloading, (5) two-spin remote tuning and exchange detection, (6) optimization of coherent conveyor-mode shuttling, (7) CROT tuning and implementation of the QND measurement framework, and (8) single- and two-qubit gate calibration.

Ancilla readout

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