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A digitally controlled silicon quantum processing unit

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Why This Matters

This breakthrough in silicon-based quantum processing units demonstrates the integration of quantum bits with industry-standard CMOS fabrication techniques, paving the way for scalable, more accessible quantum computers. By leveraging existing semiconductor manufacturing processes, this development could accelerate the adoption and commercialization of quantum technology, impacting both the tech industry and consumers seeking advanced computational capabilities.

Key Takeaways

Qubit chip

SiGe heterostructures for the qubit chip were grown on 200-mm Si wafers by chemical vapour deposition (CVD). A strain-relaxed SiGe buffer layer was grown on top of a Si wafer49, terminating with a SiGe layer that matches the Ge composition of the SiGe barriers to the quantum well. The SiGe surface of the buffer received chemical mechanical polishing to planarize the surface before CVD growth of the quantum well and barriers. The barrier layers are Si 1−x Ge x grown using SiH 4 and GeH 4 with wafer-to-wafer alloy compositions ranging from x = 0.25 to x = 0.35. The SiGe heterostructure, enriched with 28Si and depleted of 73Ge, was engineered to increase valley splitting energy50,51,52,53.

Qubit chips were fabricated on the SiGe heterostructure wafers described above, leveraging CMOS-compatible process integration. This combines the proprietary, qubit-specific front-end-of-line integration with industry-standard back-end-of-line interconnect integration. Ohmic contacts and electrically inactive regions were defined by optical lithography and ion implantation of phosphorus and argon, respectively6; no mesa etch was utilized. The qubit gate design, with a minimum feature pitch of 70 nm, was patterned with electron-beam lithography. Gate contacts and routing were formed using a self-aligned dual damascene process with a total of three minimum-pitch routing levels. At each level, designs for vias and for routing were pattern-transferred into a hard mask using electron-beam lithography. Dry etching opened vias and routing trenches within a SiO 2 interlayer dielectric. CVD tungsten (W) metallization, with a TiN liner, filled the vias and trenches, which were subsequently isolated using chemical mechanical planarization.

Next, three additional larger-pitch metal layers were formed to contact the W layers and fan out the routing lines to the pad pitch. These three layers were formed in a co-planar waveguide stack, with each layer patterned by optical lithography. Each layer was formed with a single damascene via made of W followed by a routing or ground plane layer composed of Nb using a subtractive integration. Aluminium bond pads were formed to contact the Nb routing and allow for wafer probing of the qubit devices. Following wafer probing, indium bumps were added to the aluminium pads and the wafers were diced to singulate each qubit chip for later flip-chip packaging.

Exchange-only qubits

‘Exchange only’ 1,2,3,4,5,6,7,8,9,10 means that the only physical interactions used on electrons trapped in quantum dots are (1) initialization into antisymmetric spin-singlet states, that is, \(|\uparrow \downarrow \rangle -|\downarrow \uparrow \rangle \), (2) execution of partial spin swaps \(U(\theta )=\cos (\theta /2)-i\sin (\theta /2)\times \,{\rm{S}}{\rm{W}}{\rm{A}}{\rm{P}}\), where SWAP acts between a pair of spins, and (3) pairwise measurement of singlet versus triplet (that is, \(| \uparrow \uparrow \rangle ,| \uparrow \downarrow \rangle +| \downarrow \uparrow \rangle ,| \downarrow \downarrow \rangle \)). All such interactions are available from direct-current or ‘baseband’ pulsing using the Pauli-spin blockade mechanism, which uses electrode voltages that push electrons closer to or farther from another. The resulting ‘exchange interaction’ reduces the energy of the singlet state relative to all triplet states owing to a combination of Coulomb repulsion and the Pauli-exclusion principle. No magnetic fields of any kind are required, and the entire spin system, barring errors, would maintain total spherical symmetry.

Qubits are formed from three spins in three dots using the symmetry-respecting encoding of a decoherence free subsystem1,2,3,4. The eight resultant spin states may be described in the basis denoted as \(| {S}_{12},{S};{m}\rangle \) where S 12 encodes the total spin angular momentum of the first two spins (S 12 = 0, singlet; S 12 = 1, triplet), S encodes the total spin of all three spins, and m encodes the spin projection. Ideal exchange-only initialization, logic and readout address only on the S 12 degree of freedom, and S would remain, for all encoded qubits, with constant value S = 1/2. The projection m = ±1/2 is a random and inconsequential gauge degree of freedom. Global magnetic fields B impart global phases that are also inconsequential. The angles θ for each exchange ‘gate’ U(θ), which we call exchange angles or ‘exchangles’, are determined by the time integral of the exchange energy, and as such are calibrated against direct-current voltage pulses with no direct dependence on pulse shape. Accordingly, the control of this qubit can be realized by precise switching between pairs of voltage levels—highly reminiscent of digital logic—and so is amenable to the energy-efficient cryo-control system we have described.