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An entangling gate for dual-rail erasure qubits

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To progress from the present-day era of NISQ machines14 to the era of effective quantum error correction (QEC), the performance of physical qubits and their fundamental operations must improve markedly. A useful approach to relax the requirements for QEC is to engineer qubits with structured noise, in which certain types of errors occur much more frequently than others, and to adapt the QEC scheme accordingly to take advantage of this noise. This strategy works best when the error structure is preserved as much as possible throughout all gates and measurements.

Stabilized cat qubits are an example of this model15,16,17,18,19,20, in which bit flips can be greatly suppressed relative to phase flips then allows us to concatenate these physical qubits with a repetition18 or thin rectangular surface code8,21,22,23,24 for a substantially improved QEC encoding rate.

A second way to realize this model is with erasure qubits, in which most of the errors can be detected as they occur at the hardware level10. After resetting these faulty qubits, the resulting error channel resembles a Pauli error at known spacetime location—an erasure error. QEC codes are generally more tolerant to erasures and can generally correct for twice as many erasures as Pauli errors at a given code distance5. They also possess higher thresholds as demonstrated by the surface code, which has a threshold close to 25% for phenomenological erasure noise12,13.

Erasure qubits are most often realized by detecting loss events that take us out of the computational subspace. For dual-rail qubits, such as those in photonic25,26,27,28 or superconducting platforms, this is loss of a photon or excitation that takes us to the vacuum state. In other platforms, such as neutral atoms or trapped ions, leakage to non-computational states or loss of the atom from the trap can also be detected and converted to an erasure10,29,30, with similar benefits9,31.

In superconducting circuit platforms, dual-rail qubits can be realized with pairs of transmons6,32,33,34 or microwave cavities7,35,36. When idling, dual-rail cavity qubits exhibit a strong hierarchy of errors that make them a promising erasure qubit. In this hierarchy, erasures dominate by a factor of 5–10 compared with phase flips, whereas the remaining bit flips are exceedingly rare. So far, superconducting dual-rail cavity qubits have demonstrated fast, high-fidelity single-qubit gates37,38, good state preparation and measurement (SPAM)36, and efficient, non-destructive detection of erasures39,40. However, a vital missing ingredient is an entangling operation between two dual-rail qubits, which must simultaneously have low error rates and preserve the favourable error hierarchy.

Here, we propose and experimentally demonstrate a controlled-Z (CZ) operation that satisfies these requirements for dual-rail cavity qubits. Our so-called ‘Swap–Wait–Swap’ (SWS) gate uses high-fidelity parametric operations to temporarily swap an excitation from one of the cavities (that comprise the dual-rail ‘control’ qubit) to a transmon coupler connecting the two dual-rail qubits, similar to the scheme in ref. 41. By temporarily populating the coupler, we are able to use the strong (MHz level) dispersive shift between the coupler and a cavity of the other (‘target’) dual-rail qubit. Swapping the excitation back into the control cavity completes the gate, allowing us to realize a CZ entangling gate in about 500 ns.

Importantly, our gate is bias-preserving in several aspects. The excitation-preserving nature of the gate preserves the erasure-to-Pauli noise bias on both qubits, with erasure rates below 1%. After erasure detection, we find the residual dephasing errors are at or below 0.1% per gate, as characterized by quantum state tomography (QST) and interleaved randomized benchmarking (IRB). Moreover, we also observe a strong Pauli noise bias in our gate with bit-flip errors at the order of 10−6 per CZ gate, an advantageous bias first explored theoretically in ref. 11. Moreover, target qubit erasures and dephasing rates are a factor of 3–4 times lower than those for the control qubit. This asymmetry can be carefully managed when detecting error syndromes in a QEC context (J.D.T., manuscript in preparation) to ensure errors on data qubits are minimized. Finally, we study the error channel when one of the qubits suffers from photon loss during or before the gate, and show both theoretically and experimentally that this amounts to a conditional-dephasing error on the other qubit. All of these properties can be exploited by properly designed error correction codes, as we show with simulations in the surface code (Methods). The performance levels we demonstrate are well past the predicted surface code thresholds obtained from simulations10 (J.D.T., manuscript in preparation) and should thus allow significant logical error suppression with increasing code distance.