GoKawiilEarlier this year we published a puzzle that handed you a complete neural network and asked you to figure out what it did. The response was great, so we’ve made another one! This time, we’re going much deeper down the tech stack.
For this puzzle we’ve designed a chip, but we’re only giving you the layout.
A crash course in how chips get made
Modern chips start life as code. A hardware designer describes a circuit in a hardware description language like Verilog, which gets synthesized into a netlist of logic gates—NANDs, NORs, XORs, flip-flops. Then electronic design automation tools place and route those gates: they pick a physical location for every gate on the die and draw the metal wires that connect them, across many stacked routing layers connected by vias. The end result is a GDS file: a geometric description of every polygon on every layer of the chip, from the transistors that do the actual logic to all the metal on top of them. That’s the file a foundry such as Intel or TSMC uses to fabricate the physical silicon.
The GDS is, in a very real sense, the chip. Everything the circuit does is in there. The tricky part: nothing is labeled!
The puzzle
We’ve designed an ASIC, and we’re giving you its final mask: all of its metal, routing, and active transistor layers, along with some sample inputs and outputs. Your job is to reverse engineer it. First, recover a netlist from the layout. Then figure out the circuit’s true purpose. And then comes the puzzle within the puzzle: once you understand what the chip does, use it to tease out the output it’s looking for, and find the string value that’s your final answer. You can find everything you need here. Some pointers for getting started: The circuit is physically arranged to hint at its functionality, so look closely at the layout!
There is one section of the design that is used to generate the output but does not affect the [success] output. You can safely ignore it for the initial reverse-engineering steps.
output. You can safely ignore it for the initial reverse-engineering steps. You’ll need to come up with a way to simulate the underlying circuit to test your solution and get the final output!
You’ll know you have the correct solution when the [success] output signal goes high. Don’t forget to toggle [rst_n] before each input attempt.
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