Assembly Hall of Shame

Assembly Hall of Shame

Overview

Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.

🏆 Current Champions 🏆

Strategy: Use fxrstor64 to load 512-byte FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric, then starve the fabric while the load is in flight — a fleet of hammer cores pounds a different high-latency MMIO register with tight 4-byte reads, saturating the PCIe root complex and endpoint with non-posted transactions, so CPU 0's 512-byte fxrstor64 must queue behind all that contending traffic.

Contender: AMD Ryzen 7 5800H

; CPU 0 — timed instruction movl $ 0xfcc68830 , % rsi fxrstor64 % rsi ; CPUs 1..N — hammer loop against a different high-latency location movl 0xfcc68858 , % eax

🏆 Score: 198,002,498,236 cycles

🏆 Time: 62 seconds

Honorable Mentions

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