GoKawiilThis is a version of the Project Oberon System migrated from Oberon 07 to the more common Oberon 90, using a recent version of the OP2 compiler with a RISC-V (RV32) backend; the repository also includes an emulation of a machine (VM) very similar to the one described by Wirth in his Project Oberon Book, based on the well-known RV32 emulator; the latter is a stripped-down and slightly modified version with only the interpreter, combined with my own implementation of the machine and the peripherals; the memory map of Wirth's machine is reproduced 1:1 so that Kernel.Mod, Display.Mod and Input.Mod are unchanged.
Here is a screenshot of the system running natively on the RISC-V VM:
What is the Project Oberon System 2013
As you might know, between 1986 and 1989, Niklaus Wirth and Jürg Gutknecht at ETH Zürich designed and implemented an entire computer system, including an operating system, compiler, programming language, text and graphics editors, essentially by themselves, and then documented everything in the book Project Oberon - The Design of an Operating System and Compiler (1992).
Wirth continued this journey after his retirement. The sources published on projectoberon.net are written in Oberon-07, which is Wirth's last and most radical simplification of the language. There is also a free 2013 revision of the Project Oberon book available. The declared purpose of the 2013 project is unchanged from 1992: to provide a single book that serves as an example of a system that exists, is in actual use, and is explained in all detail.
The 1992 book and project used the National Semiconductor NS32032 processor, which "is now neither available nor is its architecture recommendable". Instead of retargeting the compiler to some other commercial architecture, Wirth decided to design his own processor, which he called RISC-5, "in order to extend the desire for simplicity and regularity to the hardware". He even implemented it with a programmable gate array (FPGA) and turned his design into "a real, functioning processor on a single chip". The whole system runs on a low-cost development board (Xilinx Spartan-3 by Digilent, with 1 MB of static RAM) that "easily accommodates the entire Oberon System, including its compiler". So for the first time not only the software but also the hardware of the Oberon System is described completely and rigorously. The hardware modules are implemented in Verilog , also available on projectoberon.net.
Thanks to the simplifications of language and processor, all parts that in 1992 had been written in assembly code (and were not in the book) are now expressed in Oberon as well, from device drivers to raster operations. Wirth based his new system directly on the original Ceres version, discarding the features of the later Oberon lines. "It has been my desire to present the system essentially as it existed 25 years ago, without embellishments". The result is a small and sufficiently complete system which is well documented and easy to migrate to other architectures. The entire hardware/software contract of Project Oberon consists of a memory map plus the instruction set.
Why the migration
The name collision with RISC-V is amusing, but the kinship is real at the level of RISC design philosophy: RISC-V, developed at UC Berkeley from 2010 on, is the fifth RISC architecture of the Berkeley line (RISC-I, RISC-II, SOAR, SPUR), and both Berkeley's and Wirth's share common design goals and features: e.g. a regular 32-bit load/store, compiler-friendly ISA, with fixed 32-bit base instruction encodings.
Migrating the Project Oberon System from RISC-5 to RISC-V is a pragmatic way to bring the system to widely available contemporary hardware while preserving the principles that make Oberon valuable. Espressif offers inexpensive, readily available microcontrollers in several ESP32 families, and board makers such as Olimex build practical development boards around them, for example the ESP32-P4-PC which provides all resources needed by the Oberon System at a very attractive price. Since the Oberon system does not require an MMU, it is well-suited for this type of microcontroller. So far, this migration runs on an emulated RISC-V machine, which helps both debugging and keeping the code close to the book. Future iterations will migrate this (and also System 3) to the mentioned Olimex board.
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