GoKawiilThe PCIe 6.0 specification was ratified in early 2022, but its actual implementation was delayed for years. Now, the spec is almost ready, with the first PCIe Gen6 platforms finally approaching, as are actual storage devices. Micron was the first with a PCIe 6 SSD in mid-2025, and Samsung caught up this July. Meanwhile, independent makers of SSD controllers — Marvell, Phison, and Silicon Motion — are also prepping their PCIe 6 SSD platforms.
For a full roadmap of PCIe, you can check out our dedicated page. In this article, we'll specifically focus on PCIe 6.0 controllers and devices and how they're soon becoming commercial products. For additional reading, you can also find our interview with Solidigm VP Avi Shetty, which covers the subject of PCIe 6.0 SSDs.
Per ardua ad astra
PCIe 1.0 through 5.0 used simple NRZ signaling (one bit per signal) with 128b/130b encoding, which was relatively simple to implement at the controller level. However, it required some complicated methods to ensure signal integrity at 32 GT/s per lane.
Latest Videos From Tom's Hardware Watch full video here:
PCIe 6.0 now adopts PAM4 signaling (which encodes two bits per symbol using four voltage levels), which keeps the physical signaling rate at 32 Gbaud. However, it also doubles the effective transfer rate to 64 GT/s by transmitting two bits per signal instead of one. As a result, transmitter and receiver design became considerably more complicated, as it required sophisticated DSPs, equalization, FEC, and CRC-based retry mechanisms, which complicated the development of PCIe 6.0 controllers. Furthermore, PCIe 6.0 often requires retimers where PCIe 5.0 did not, which complicated the development of actual servers.
(Image credit: Future)
To make matters even more complicated, every new PCIe generation requires interoperability testing among CPUs, GPUs, SSDs, network cards, switches, retimers, and other devices from dozens of vendors. Since PAM4 behaves very differently from NRZ, PCI-SIG had to develop entirely new compliance procedures, test equipment, and interoperability programs. The development of those programs themselves slipped, which greatly delayed any commercial deployment. The very first PCIe 6 interoperability testing at 64 GT/s took place in late July.
Despite formidable implementation hurdles and interoperability program challenges, PCIe 6 is finally making its way into commercial platforms. AMD's 6th Generation EPYC 'Venice' and Nvidia's Vera CPUs fully support PCIe Gen6, so companies from the adjacent industry sectors are catching up with their PCIe 6 products, and storage makers are among them.
For storage, PCIe 6.0 doubles host interface bandwidth to around 30.25 GB/s for a x4 link without the protocol's overhead (which is not that big with the 1b/1b 242B/256B FLIT encoding featured by PCIe 6). The new interconnect does not improve flash operation on its own. Meanwhile, PAM4 introduces Forward Error Correction (FEC), which slightly increases latency, but it also enables doubling throughput without doubling the signaling frequency to 64 Gbaud.
... continue reading