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After teasing the chips earlier this year, Intel has provided some details on its next-gen Xeon 7, codenamed Diamond Rapids, CPUs. Featuring up to 256 P-cores and 1.28 GB of last-level cache, the new range of CPUs is set to release in the data center in 2027. The range brings forth several advancements we've expected on Intel's roadmap, including the enhanced 18A-P process, UCIe interconnects, AVX 10.2, and Intel's new "fan-out" fabric.
Intel didn't detail the core architecture (known as Panther Cove) in Diamond Rapids during its Hot Chips 2026 presentation, so we'll likely have at least one more technical deep dive on Diamond Rapids before it arrives, and possibly more. Although there are still questions about Panther Cove, Intel shared a technical breakdown of how Diamond Rapids chips are built more broadly, including a look at the compute tiles and how they come together across the chip.
Intel calls the compute tiles Compute Building Blocks, or CBBs, and they hold the core chiplet stacked on top of the base tile that holds the LLC. Each core chiplet can hold up to 16 cores, and based on the scaled-up Diamond Rapids SoC, up to four of those chiplets can live in a CBB. Each chiplet connects to the base tile with a 3D Xbar. A full Diamond Rapids SoC includes four base tiles built on Intel 3-T, two fabric hub tiles built on Intel 3, and 16 core chiplets built on Intel 18A-P.
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Bringing everything together are two advanced packaging techniques. Intel is once again using its own Foveros Direct 3D to bond the compute tiles to the base tiles, as seen with Xeon 6+ 'Clearwater Forest' CPUs. Intel is using UCIe-S to connect the fabric hub tiles to the cores via a copper connection. Notably, Intel isn't using its own Embedded Multi-die Interconnect Bridge (EMIB) that it's broadly deployed in past products.
Intel Xeon 7 'Diamond Rapids' compute chiplet
(Image credit: Intel)
Diamond Rapids is built with four Compute Building Blocks, each of which includes four core chiplets that house 16 P-cores each. The cores have access to private L2 within each chiplet, and they share an L3 cache located on the base tile. The chiplets are connected to the base tile with a 3D crossbar, packaged with Foveros Direct 3D.
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