GoKawiilIntel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.
One million High-NA wafers
Intel's one million wafers figure includes wafers processed during tool installation and certification, R&D, and production. Earlier this year, Intel certified using High-NA EUV scanners for its 18A process technology, so right now these tools are used to make some of Intel's Panther Lake processors. Intel currently has two ASML Twinscan EXE:5000 tools and at least one EXE:5200B scanner. As of late February 2025, Intel processes around 30,000 wafers using its High-NA EUV tool, so going from 30,000 wafers by February 2025 to over a million by September 2026 is an enormous increase in cumulative High-NA utilization.
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Since Intel's fleet expanded from two EXE:5000 systems to three and now includes the much faster EXE:5200B, the million-wafer milestone is really a fleet and process-maturity milestone that Intel has achieved first in the industry. What makes the company's milestone even more important is that ASML announced this April that all of the High-NA EUV scanners shipped by then processed over 500,000 wafers which achieving over 80% availability, which means that Intel has now processed more wafers using High-NA tools than the rest of the industry combined.
Sticking to stitching
Conventional 0.33-NA EUV has 4X magnification in both directions, enabling the familiar 26×33 mm exposure field with traditional 6-inch photomasks. However, 0.55-NA EUV uses anamorphic 4X/8X magnification, so the same 6×6 mask can provide only approximately 26×16.5 mm on the wafer. As a result, large dies that fit within a conventional 26 × 33 mm EUV field must be exposed as two half-fields using High-NA EUV, which is called stitching. While stitching is a workable near-term solution, it has several drawbacks.
(Image credit: ASML)
Firstly, it greatly reduces throughput from 175 wafers per hour to 125 wafers per hour on an EXE:5200B. Secondly, chip designs must account for stitching and must be developed with stitching in mind, which means less floor planning freedom. Thirdly, the two exposures must be aligned extremely precisely so that features crossing the stitching boundary connect properly. Even a tiny misalignment can distort lines and vias, or break interconnects, which potentially creates defects and reduces yields, which will be a particularly costly problem for large CPU and GPU dies.
6×12 mask effort progressing
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