TSMC revealing details about next gen A14 node

2026-09-15 | original

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Why This Matters

TSMC's disclosure of A14 node details signals the next major leap in chip manufacturing after N2, promising significant gains in speed, power efficiency, and density that will shape future high-end chips from Apple, AMD, Nvidia and others. This matters because these process advances underpin performance improvements across smartphones, PCs, and AI hardware for years to come.

Key Takeaways

A14 delivers 10-15% speed gains and 25-30% power reduction over N2, with ~20% higher chip density
New SRAM cell design achieves the industry's smallest size and highest macro density via dimensional scaling
Advanced packaging features like TSV and 4.5μm SoIC bond pitch aim to boost system-level integration, with volume production targeted for 2028

Abstract

A14 NanoFlexTM Pro platform technology features the world’s smallest SRAM with a cell size <0.017μm2 and highest SRAM macro density to date through dimensional ground rule scaling. Coupled with standard cell innovations, it delivers a full-node PPA improvement over the predecessor N2 technology for a 10~15% speed enhancement, a 25~30% power reduction and a chip density increase by ~20% driven by logic and SRAM scaling. Key features, such as TSV, innovative RDL that enables SoIC bond pitch of 4.5μm and high-performance MiM processes, have also been developed to accelerate the system-level integration and scaling for SoIC products. Supported by robust yield and device progress, A14 technology is on track for volume production in 2028.

Explore topics: a14 node tsmc nanoflex pro soic sram scaling