C. Scott Brown / Android Authority
TL;DR Qualcomm is working on a new wearable chip, the “SW6100”, also called “aspena”
The processor is not based on any previous Qualcomm product, unlike its previous wearable chips
The specs include 1x Arm Cortex-A78 + 4x Arm Cortex-A55, an LPDDR5X RAM controller, all built on a TSMC process node
Wear OS smartwatches have been in a bit of a standstill lately. After releasing Snapdragon W5/+ Gen 1 in 2022, Qualcomm hasn’t given the platform any attention, with only Samsung continuing to develop new chips for wearables. Google smartwatches, for example, have been stuck on the same Qualcomm platform for three years now. There was some talk about possible RISC-V-based SoCs as well as next-generation chips for a while now, but without any concrete details.
That is, until now. Android Authority has viewed credible evidence that Qualcomm is working on a new wearables platform and some of its specs. If it does see the light of day, it could give the next generation of Wear OS wearables a much-needed performance jump.
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Kamila Wojciechowska / Android Authority Qualcomm Snapdragon Wear 4100 reference design from my collection
Historically, Qualcomm’s wear chips haven’t received the same attention to detail as its smartphone models. They are often existing smartphone chips with minor modifications, and some are also built on a newer process node. In fact, some of the earlier reference designs Qualcomm provides to OEMs use unmodified smartphone chips! Of course, some work still goes into them (like optimizing sensor hubs and wireless), but a fully bespoke design has never been a priority for Qualcomm. The only fully custom part of the platform was the external coprocessor chips, but even those were built in the cheapest way possible, utilizing a lot of off-the-shelf IP.
For example, Snapdragon W5+ Gen 1’s QCC5100 coprocessor utilizes an Arm-designed Ethos ML core, Cadence’s HiFi 5 DSP and Think Silicon’s Nema|pico 2.5D GPU, even though Qualcomm has its own cores to do all of these functions and scaling them down for use in a coprocessor is perfectly possible.
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