AMD Epyc 'Venice' will be built on TSMC's N2 node, 5th-gen Epyc to be fabbed in Arizona

In a nutshell: The 6th-generation AMD Epyc processors, codenamed Venice, will be the first high-performance computing product built using TSMC's 2nm (N2) process node. Team Red also confirmed that TSMC's new Fab 21 facility in Arizona has successfully validated 5th-generation Epyc silicon and will handle some of the chip production in the United States. Venice, built on AMD's upcoming Zen 6 microarchitecture, represents a major milestone in the company's data center roadmap and remains on track for release next year. While AMD withheld further details, it confirmed the silicon has been taped out and brought up – indicating the CCD powered on successfully and passed initial tests. Leaked details indicate that Epyc Venice CPUs will use the new SP7 socket, replacing the SP6 (LGA 4094) platform in Zen 4c-based Siena processors. Rumors also point to support for both 12-channel and 16-channel memory configurations, along with faster DIMM speeds on the PCIe Gen 6 interface. The new N2 proc ... Read full article.