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SK hynix delays hybrid bonding for HBM until HBM5, cites 775-micron package limit

At Hot Chips 2026, SK hynix's Jaesik Lee said hybrid bonding won't be ready in time for HBM4E and will instead debut with HBM5, as current HBM4 packages are already constrained by a 775-micron thickness ceiling matching standard logic wafers. To keep scaling within that limit, 16-Hi HBM4 stacks now use dies thinned to about 50 microns with half the interlayer gap of 12-Hi designs, while SK hynix continues using its existing MR-MUF bonding method through upcoming Nvidia Rubin-generation products.

Marvell unveils three-tier AI memory lineup and new PCIe 6.0 SSD controller amid DRAM crunch

At FMS 2026, Marvell pitched a three-part 'AI memory infrastructure' strategy built around CXL, combining its Structera X memory expansion controllers, the Structera S switch, and the Photonic Fabric optical tier from its Celestial AI acquisition. Only the Bravera SC6 PCIe 6.0 SSD controller, sampling in Q4 2026, is genuinely new; the rest has already been shipping or announced over the past two years, with Marvell VP Khurram Malik highlighting reused DDR4 memory paired with CXL as a top use case.

Researcher uses Claude Opus 5 to reverse-engineer firmware in mic, webcam, key light

An engineer spent two weeks pointing an AI coding agent, Claude Opus 5, at the firmware and update tools of everyday USB peripherals—a microphone, a webcam, and a key light. The agent extracted a full command shell from the microphone, found a way to disable the webcam's recording LED while it still captures video, and discovered the key light accepts unauthenticated memory writes from any device on the same WiFi network.

Nvidia to hike AI server prices over 15% amid memory shortage

Nvidia has informed top customers that server systems built around its Grace Blackwell and Vera Rubin AI chips will cost more than 15% extra when they ship early next year, according to a Bloomberg report. Contract manufacturers serving Microsoft, Google, and Oracle have already passed along the increases, which vary by chip generation and memory configuration.

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