Disrupting the DRAM roadmap with capacitor-less IGZO-DRAM technology
A novel DRAM memory cell with two IGZO-based transistors The bit cell of dynamic random-access memory (DRAM), the main memory within traditional compute architectures, is conceptually very simple. It consists of one capacitor (1C) and one silicon (Si)-based transistor (1T). While the capacitor’s role is to store a charge, the transistor is used to access the capacitor, either to read how much charge is stored or to store a new charge. Over the years, bit cell density scaling allowed the indust