SUS Lang: The SUS Hardware Description Language
The compiler keeps track of many aspects of your hardware design, and displays them in the editor. Core Philosophy The SUS HDL is meant to be a direct competitor to Synthesizeable Verilog and VHDL. Its main goal is to be an intuitive and thin syntax for building netlists, such that traditional synthesis tools can still be used to analyze the resulting hardware. SUS shall impose no paradigm on the hardware designer, such as requiring specific communication protocols or iteration constructs. In