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XLS: Accelerated HW Synthesis (news.ycombinator.com)

2026-09-14 | tags: xls, high-level synthesis, verilog

Trying to preserve other peoples code (news.ycombinator.com)

2026-05-23 | get GitHub Copilot Subscription → | tags: verilog, vhdl, crc

I designed a nibble-oriented CPU in Verilog to build a scientific calculator (news.ycombinator.com)

2026-05-15 | get Scientific Calculator Kit → | tags: verilog, fpga, quartus

Circuit-level PDP-11/34 emulator (news.ycombinator.com)

2026-03-28 | tags: pdp-11/34, unibus, verilog

A Verilog to Factorio Compiler and Simulator (Working RISC-V CPU) (news.ycombinator.com)

2026-03-26 | tags: verilog, factorio, risv

Vectorization of Verilog Designs and its Effects on Verification and Synthesis (news.ycombinator.com)

2026-03-19 | get Verilog Design Verification Kit → | tags: verilog, vectorization, verification

SUS Lang: The SUS Hardware Description Language (news.ycombinator.com)

2025-10-31 | get computer monitor → | tags: design, hardware, impose

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