I designed a nibble-oriented CPU in Verilog to build a scientific calculator

From Gates to a Calculator

This project implements a fully functional scientific calculator in hardware using an FPGA. It includes a custom soft CPU, microcode firmware, and supporting tools.

For the full story, see the blog.

Try it in a web browser:

Project Structure

Folder Description verilog/ SystemVerilog source files for the CPU, ALU, I/O, and test benches ucode/ Microcode (firmware) for the soft CPU quartus/ Quartus project files for FPGA synthesis modelsim/ ModelSim simulation setup Qt/ Qt-based simulator and debugger (uses Verilator) calctest/ Command-line test harness for hardware verification (uses Verilator) tools/ Assembler and script compiler for the microcode Pathfinding/ Algorithm research and verification projects

Quick Start

The fastest way to try the calculator is to build the Qt simulator:

# From WSL2 cd /mnt/c/Projects/FPGA-Calculator/verilog make qt

Then open Qt/Calculator.pro in Qt Creator and build for "Desktop Qt MSVC2022 64 Bit".

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