XLS: Accelerated HW Synthesis

What is XLS?

XLS implements a High Level Synthesis toolchain that produces synthesizable designs (Verilog and SystemVerilog) from flexible, high-level descriptions of functionality. It is Apache 2 licensed.

XLS (Accelerated HW Synthesis) aims to be the Software Development Kit (SDK) for the End of Moore's Law (EoML) era. In this "age of specialization", software and hardware engineers must do more co-design across their domain boundaries -- collaborate on shared artifacts, understand each other's cost models, and share tooling/methodology. XLS attempts to leverage automation, software engineers, and machine cycles to accelerate this overall process.

XLS enables the rapid development of hardware IP that also runs as efficient host software via "software style" methodology. An XLS design runs at native speeds for use in host software or a simulator, but that design can also generate hardware block output -- the XLS tools' correctness ensures (and provides tools to help formally verify) that they are functionally identical.

XLS supports both (optionally pipelined) functions with pure-wire I/O interfaces and concurrent processes (or proc s). Procs are stateful, allowing induction over time, and include more general communication interfaces.

State of the Project

XLS is experimental, undergoing rapid development, and not an officially supported Google product. Expect bugs and sharp edges. Please help by trying it out, running through some tutorials, reporting bugs.

We are early stage and this has some practical effects:

We welcome your issues and PRs. - Please try to lead with an issue. Engage us in conversation if you wish to upstream changes. Sending a PR without back and forth with us in an issue may be a longer road to success. If you believe your PR is ready and has not received a response within two business days, please ping the issue with what you think are next steps.

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