GoKawiilGoogle open-sources XLS, a high-level synthesis toolchain for hardware design
Google has released XLS, an Apache 2.0-licensed toolchain that converts high-level functional descriptions into synthesizable Verilog and SystemVerilog hardware designs. The tool lets engineers write logic once and run it both as native host software and as generated hardware, with correctness guarantees ensuring the two versions behave identically.
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As Moore's Law slows, chip specialization is becoming essential, and XLS is designed to help software and hardware engineers collaborate more directly on shared code rather than separate toolchains. By letting the same design run as software or synthesize into hardware, it could speed up custom silicon development cycles, though Google warns the project is still experimental and not production-supported.
- XLS converts high-level code into synthesizable Verilog/SystemVerilog hardware designs.
- It supports both pipelined functions and stateful concurrent processes for hardware description.
- The project is early-stage, open-source under Apache 2.0, and not an official Google product.
Source: google.github.io, 2026-09-14
Published there as: “XLS: Accelerated HW Synthesis”
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