GoKawiilStudent builds out-of-order RISC-V CPU core named Specula
A fourth-semester engineering student built Specula, an out-of-order RV32I processor written in Bluespec SystemVerilog, as a self-directed side project. The student says the project began after discovering their Ryzen 9 laptop chip used out-of-order execution, prompting them to attempt replicating similar complexity from scratch while still learning the Bluespec language.
GoKawiil's interpretation of the reporting above, not reported fact.
The project illustrates how individual learners are tackling advanced computer architecture concepts, like out-of-order execution and hazard handling, outside formal coursework, often using open hardware description tools such as Bluespec. It also reflects the growing accessibility of RISC-V as a platform for experimenting with processor design that was once confined to major chipmakers.
- Specula is a self-built out-of-order RV32I RISC-V processor core.
- It is written in Bluespec SystemVerilog, a language the developer was still learning.
- The project grew out of independent curiosity about how CPUs like the Ryzen 9 handle instruction execution.
Source: prawns.dev, 2026-11-06
Published there as: “Building an Order RISC-V CPU from scratch”
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